On Mon, 15 Apr 2024 16:03:37 +0100, Caleb Connolly wrote:
> The msm serial UART controller has a bit clock divider register which
> much be programmed based on the UART clock. This changes per soc and
> currently is expected to be specified in DT or otherwise selected per
> board.
>
> This series fixes the apq8016 and ipq4019 clock drivers to return the
> programmed UART clock rate in clk_set_rate(), it then uses this clock
> rate and the hardcoded baud rate supported by this driver to calculate
> the correct value for the UARTDM_CSR register.
>
> [...]
Applied, thanks!
[1/3] clk/qcom: apq8016: return valid rate when setting UART clock
commit: f191853d77899c8a845f20f62068c4ee68d2a020
[2/3] clk/qcom: ipq4019: return valid rate when setting UART clock
commit: b49b68909b5f4030869051073857d086c5292461
[3/3] serial: msm: calculate bit clock divider
commit: 1aadf1ebc32c8bf7f4eae9ab2abaf63c1fea7d4f
Best regards,
--
// Caleb (they/them)
