Add dummy support for setting parent of USB480M clock. Signed-off-by: Jonas Karlman <jo...@kwiboo.se> --- v2: No change --- drivers/clk/rockchip/clk_rk3308.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 7515fc8bb244..c46b58e31626 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -1085,6 +1085,8 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) case SCLK_RTC32K: ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); break; + case USB480M: + return 0; default: return -ENOENT; } @@ -1117,6 +1119,8 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par switch (clk->id) { case SCLK_MAC: return rk3308_mac_set_parent(clk, parent); + case USB480M: + return 0; default: break; } -- 2.43.2