HI On Fri, Mar 22, 2024 at 1:02 PM Alexander Dahl <a...@thorsis.com> wrote: > > Hello Michael, > > Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi: > > HI > > > > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <a...@thorsis.com> wrote: > > > > > > Hello Mihai, > > > > > > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb mihai.s...@microchip.com: > > > > Hi Michael, > > > > > > > > ------------------------------------------------------- > > > > > > > > I think this command can be really useful. > > > > Let try to have more testing on more boards > > > > > > > > --------------------------------------------------------- > > > > > > > > I managed to test the command on sama7g54-curiosity board. > > > > > > Thanks for that. Nice to see it works on other variants of the SoC > > > family. > > > > > > > I also forced timing mode 5 from controller driver > > > > (conf->timings.sdr.tRC_min < 20000). > > > > > > You did a similar thing for the sam9x75. These boards/socs seem to > > > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > > > driver claims all the (H)SMC incarnations do _not_ support these EDO > > > modes 4 and 5. Maybe someone could have a deeper look at the > > > datasheets of the newer SoCs and propose a patch to support those > > > newer controllers in the atmel nand-controller driver? I guess the > > > problem is the same in Linux, right? > > > > > > Greets > > > Alex > > > > > > > > > > > => nand onfi 0 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3: 0x00000004 > > > > HSMC_PULSE3: 0x140a140a > > > > HSMC_CYCLE3: 0x00140014 > > > > HSMC_TIMINGS3: 0x880805f4 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > > (100 ns) > > > > NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 > > > > (100 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > > (100 ns) > > > > NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 > > > > (100 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 64 (320 ns) > > > > TAR (ALE to REN Low Delay): 5 (25 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size > > > > 0x40000) > > > > Passed: 64, failed: 0 > > > > > > > > time: 22.638 seconds > > > > > > > > => nand onfi 5 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3: 0x00000001 > > > > HSMC_PULSE3: 0x07040502 > > > > HSMC_CYCLE3: 0x00070005 > > > > HSMC_TIMINGS3: 0x880402f2 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 > > > > ns) > > > > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 > > > > (35 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 > > > > ns) > > > > NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 > > > > (25 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 4 (20 ns) > > > > TAR (ALE to REN Low Delay): 2 (10 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size > > > > 0x40000) > > > > Passed: 64, failed: 0 > > > > > > > > time: 11.661 seconds > > > > > > > > => nand info > > > > > > > > Device 0: nand0, sector size 256 KiB > > > > Manufacturer MACRONIX > > > > Model MX30LF4G28AD > > > > Device size 512 MiB > > > > Page size 4096 b > > > > OOB size 256 b > > > > Erase size 262144 b > > > > ecc strength 8 bits > > > > ecc step size 512 b > > > > subpagesize 4096 b > > > > options 0x40004200 > > > > bbt options 0x00028000 > > > > > > > > Best regards, > > > > Mihai Sain > > > > I'm in favor to have it even cover by one soc family. I would like to > > confirm on imx6 and imx8. If you are not in a rush. > > Let's us test too > > Agreed. This is a generic nand command, so it would of course be > reasonable to test it on multiple nand controllers. I'm afraid I > currently have only at91 boards on my desk for which I have a recent > U-Boot _and_ a NAND chip soldered. So take your time for this patch. > > If you don't mind I would be happy if you could merge the four trivial > patches which do not add new features and which already got your > reviewed-by in the next cycle already, and let those other patches > with the new subcommands for debugging be tested as long as needed. >
I think Dario already queue them Michael > Kind regards > Alex > > > > > Michael > > > > -- > > Michael Nazzareno Trimarchi > > Co-Founder & Chief Executive Officer > > M. +39 347 913 2170 > > mich...@amarulasolutions.com > > __________________________________ > > > > Amarula Solutions BV > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > T. +31 (0)85 111 9172 > > i...@amarulasolutions.com > > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
