On Tue, 19 Mar 2024 at 17:52, Caleb Connolly <caleb.conno...@linaro.org> wrote:
>
> Most devices only initialise the USB clocks for us if we boot via
> "fastboot boot", add the missing clock configuration to get both USB
> ports working regardless of the bootloader state.
>
> Signed-off-by: Caleb Connolly <caleb.conno...@linaro.org>
> ---
> drivers/clk/qcom/clock-sdm845.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
Reviewed-by: Sumit Garg <sumit.g...@linaro.org>
-Sumit
> diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
> index b7154360894a..e9c61eb480de 100644
> --- a/drivers/clk/qcom/clock-sdm845.c
> +++ b/drivers/clk/qcom/clock-sdm845.c
> @@ -20,8 +20,12 @@
> #include "clock-qcom.h"
>
> #define SE9_UART_APPS_CMD_RCGR 0x18148
>
> +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
> +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
> +
> static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> @@ -56,8 +60,10 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong
> rate)
> }
> }
>
> static const struct gate_clk sdm845_clks[] = {
> + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001),
> + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001),
> GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400),
> GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800),
> GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000),
> GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000),
> @@ -120,8 +126,27 @@ static int sdm845_clk_enable(struct clk *clk)
> struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>
> debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
>
> + switch (clk->id) {
> + case GCC_USB30_PRIM_MASTER_CLK:
> + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
> + /* These numbers are just pulled from the frequency tables in
> the Linux driver */
> + clk_rcg_set_rate_mnd(priv->base,
> USB30_PRIM_MASTER_CLK_CMD_RCGR,
> + (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
> + clk_rcg_set_rate_mnd(priv->base,
> USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
> + 1, 0, 0, 0, 8);
> + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
> + 1, 0, 0, 0, 8);
> + break;
> + case GCC_USB30_SEC_MASTER_CLK:
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
> +
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
> + break;
> + }
> +
> qcom_gate_clk_en(priv, clk->id);
>
> return 0;
> }
>
> --
> 2.44.0
>
