On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<volodymyr_babc...@epam.com> wrote:
>
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babc...@epam.com>
>
> ---
>
> Changes in v2:
> - Reworked qcom_cc_bind() function
> - Added timeout to qcom_power_set()
> - Minor fixes in register names and formatting
>
> drivers/clk/qcom/clock-qcom.c | 128 ++++++++++++++++++++++++++++++----
> drivers/clk/qcom/clock-qcom.h | 6 ++
> 2 files changed, 121 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 729d190c54..c3f8d96183 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -23,6 +23,7 @@
> #include <linux/delay.h>
> #include <linux/bitops.h>
> #include <reset-uclass.h>
> +#include <power-domain-uclass.h>
>
> #include "clock-qcom.h"
>
> @@ -30,6 +31,13 @@
> #define CBCR_BRANCH_ENABLE_BIT BIT(0)
> #define CBCR_BRANCH_OFF_BIT BIT(31)
>
> +#define GDSC_SW_COLLAPSE_MASK BIT(0)
> +#define GDSC_POWER_DOWN_COMPLETE BIT(15)
> +#define GDSC_POWER_UP_COMPLETE BIT(16)
> +#define GDSC_PWR_ON_MASK BIT(31)
> +#define CFG_GDSCR_OFFSET 0x4
> +#define GDSC_STATUS_POLL_TIMEOUT_US 1500
> +
> /* Enable clock controlled by CBC soft macro */
> void clk_enable_cbc(phys_addr_t cbcr)
> {
> @@ -223,7 +231,7 @@ U_BOOT_DRIVER(qcom_clk) = {
> int qcom_cc_bind(struct udevice *parent)
> {
> struct msm_clk_data *data = (struct msm_clk_data
> *)dev_get_driver_data(parent);
> - struct udevice *clkdev, *rstdev;
> + struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
> struct driver *drv;
> int ret;
>
> @@ -238,20 +246,41 @@ int qcom_cc_bind(struct udevice *parent)
> if (ret)
> return ret;
>
> - /* Bail out early if resets are not specified for this platform */
> - if (!data->resets)
> - return ret;
> + if (data->resets) {
> + /* Get a handle to the common reset handler */
> + drv = lists_driver_lookup_name("qcom_reset");
> + if (!drv) {
> + ret = -ENOENT;
> + goto unbind_clkdev;
> + }
> +
> + /* Register the reset controller */
> + ret = device_bind_with_driver_data(parent, drv, "qcom_reset",
> (ulong)data,
> + dev_ofnode(parent),
> &rstdev);
> + if (ret)
> + goto unbind_clkdev;
> + }
>
> - /* Get a handle to the common reset handler */
> - drv = lists_driver_lookup_name("qcom_reset");
> - if (!drv)
> - return -ENOENT;
> + if (data->power_domains) {
> + /* Get a handle to the common power domain handler */
> + drv = lists_driver_lookup_name("qcom_power");
> + if (!drv) {
> + ret = -ENOENT;
> + goto unbind_rstdev;
> + }
> + /* Register the power domain controller */
> + ret = device_bind_with_driver_data(parent, drv, "qcom_power",
> (ulong)data,
> + dev_ofnode(parent),
> &pwrdev);
> + if (ret)
> + goto unbind_rstdev;
> + }
>
> - /* Register the reset controller */
> - ret = device_bind_with_driver_data(parent, drv, "qcom_reset",
> (ulong)data,
> - dev_ofnode(parent), &rstdev);
> - if (ret)
> - device_unbind(clkdev);
> + return 0;
> +
> +unbind_rstdev:
> + device_unbind(rstdev);
> +unbind_clkdev:
> + device_unbind(clkdev);
>
> return ret;
> }
> @@ -306,3 +335,76 @@ U_BOOT_DRIVER(qcom_reset) = {
> .ops = &qcom_reset_ops,
> .probe = qcom_reset_probe,
> };
> +
> +static int qcom_power_set(struct power_domain *pwr, bool on)
> +{
> + struct msm_clk_data *data = (struct msm_clk_data
> *)dev_get_driver_data(pwr->dev);
> + void __iomem *base = dev_get_priv(pwr->dev);
> + unsigned long timeout;
> + const struct qcom_power_map *map;
> + u32 value;
> +
> + if (pwr->id >= data->num_power_domains)
> + return -ENODEV;
> +
> + map = &data->power_domains[pwr->id];
> +
> + if (!map->reg)
> + return -ENODEV;
> +
> + value = readl(base + map->reg);
> +
> + if (on)
> + value &= ~GDSC_SW_COLLAPSE_MASK;
> + else
> + value |= GDSC_SW_COLLAPSE_MASK;
> +
> + writel(value, base + map->reg);
> +
> + timeout = timer_get_us() + GDSC_STATUS_POLL_TIMEOUT_US;
> + /* Wait for power on */
> + while (timeout > timer_get_us()) {
> + value = readl(base + map->reg + CFG_GDSCR_OFFSET);
You should be able to reuse readl_poll_timeout() here instead.
-Sumit
> + if (on) {
> + if ((value & GDSC_POWER_UP_COMPLETE) ||
> + (value & GDSC_PWR_ON_MASK))
> + return 0;
> + } else {
> + if (value & GDSC_POWER_DOWN_COMPLETE ||
> + !(value & GDSC_PWR_ON_MASK))
> + return 0;
> + }
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int qcom_power_on(struct power_domain *pwr)
> +{
> + return qcom_power_set(pwr, true);
> +}
> +
> +static int qcom_power_off(struct power_domain *pwr)
> +{
> + return qcom_power_set(pwr, false);
> +}
> +
> +static const struct power_domain_ops qcom_power_ops = {
> + .on = qcom_power_on,
> + .off = qcom_power_off,
> +};
> +
> +static int qcom_power_probe(struct udevice *dev)
> +{
> + /* Set our priv pointer to the base address */
> + dev_set_priv(dev, (void *)dev_read_addr(dev));
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(qcom_power) = {
> + .name = "qcom_power",
> + .id = UCLASS_POWER_DOMAIN,
> + .ops = &qcom_power_ops,
> + .probe = qcom_power_probe,
> +};
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 01088c1901..12a1eaec2b 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -59,9 +59,15 @@ struct qcom_reset_map {
> u8 bit;
> };
>
> +struct qcom_power_map {
> + unsigned int reg;
> +};
> +
> struct clk;
>
> struct msm_clk_data {
> + const struct qcom_power_map *power_domains;
> + unsigned long num_power_domains;
> const struct qcom_reset_map *resets;
> unsigned long num_resets;
> const struct gate_clk *clks;
> --
> 2.43.0
