Drop in favour of dts/upstream.
Small driver/dts change to fix compatibility.
Signed-off-by: Caleb Connolly <caleb.conno...@linaro.org>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 26 +++++++++++++-------------
drivers/clk/sifive/fu540-prci.c | 8 ++++----
include/dt-bindings/clock/sifive-fu540-prci.h | 18 ------------------
include/dt-bindings/clock/sifive-fu740-prci.h | 24 ------------------------
4 files changed, 17 insertions(+), 59 deletions(-)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 360679a1781a..0f8181436410 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -6,42 +6,42 @@
#include <dt-bindings/reset/sifive-fu540-prci.h>
/ {
cpus {
- assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clocks = <&prci FU540_PRCI_CLK_COREPLL>;
assigned-clock-rates = <1000000000>;
bootph-pre-ram;
cpu0: cpu@0 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
bootph-pre-ram;
};
};
cpu1: cpu@1 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
bootph-pre-ram;
cpu1_intc: interrupt-controller {
bootph-pre-ram;
};
};
cpu2: cpu@2 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
bootph-pre-ram;
cpu2_intc: interrupt-controller {
bootph-pre-ram;
};
};
cpu3: cpu@3 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
bootph-pre-ram;
cpu3_intc: interrupt-controller {
bootph-pre-ram;
};
};
cpu4: cpu@4 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
bootph-pre-ram;
cpu4_intc: interrupt-controller {
bootph-pre-ram;
};
@@ -66,22 +66,22 @@
bootph-pre-ram;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
- resets = <&prci PRCI_RST_DDR_CTRL_N>,
- <&prci PRCI_RST_DDR_AXI_N>,
- <&prci PRCI_RST_DDR_AHB_N>,
- <&prci PRCI_RST_DDR_PHY_N>,
- <&prci PRCI_RST_GEMGXL_N>;
+ resets = <&prci FU540_PRCI_RST_DDR_CTRL_N>,
+ <&prci FU540_PRCI_RST_DDR_AXI_N>,
+ <&prci FU540_PRCI_RST_DDR_AHB_N>,
+ <&prci FU540_PRCI_RST_DDR_PHY_N>,
+ <&prci FU540_PRCI_RST_GEMGXL_N>;
reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
"ddr_phy", "gemgxl_reset";
};
dmc: dmc@100b0000 {
compatible = "sifive,fu540-c000-ddr";
reg = <0x0 0x100b0000 0x0 0x0800
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>;
- clocks = <&prci PRCI_CLK_DDRPLL>;
+ clocks = <&prci FU540_PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
bootph-pre-ram;
};
};
@@ -99,9 +99,9 @@
bootph-pre-ram;
};
ð0 {
- assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+ assigned-clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125000000>;
};
&l2cache {
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index ceb2c6fab0da..b019f682ac49 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -58,27 +58,27 @@ static const struct __prci_clock_ops
sifive_fu540_prci_tlclksel_clk_ops = {
};
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu540[] = {
- [PRCI_CLK_COREPLL] = {
+ [FU540_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data,
},
- [PRCI_CLK_DDRPLL] = {
+ [FU540_PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
- [PRCI_CLK_GEMGXLPLL] = {
+ [FU540_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data,
},
- [PRCI_CLK_TLCLK] = {
+ [FU540_PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h
b/include/dt-bindings/clock/sifive-fu540-prci.h
deleted file mode 100644
index 6a0b70a37d78..000000000000
--- a/include/dt-bindings/clock/sifive-fu540-prci.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018-2019 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- */
-
-#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
-#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
-
-/* Clock indexes for use by Device Tree data and the PRCI driver */
-
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_TLCLK 3
-
-#endif
diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h
b/include/dt-bindings/clock/sifive-fu740-prci.h
deleted file mode 100644
index 672bdadbf6c0..000000000000
--- a/include/dt-bindings/clock/sifive-fu740-prci.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2019 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- * Zong Li
- */
-
-#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
-#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
-
-/* Clock indexes for use by Device Tree data and the PRCI driver */
-
-#define FU740_PRCI_CLK_COREPLL 0
-#define FU740_PRCI_CLK_DDRPLL 1
-#define FU740_PRCI_CLK_GEMGXLPLL 2
-#define FU740_PRCI_CLK_DVFSCOREPLL 3
-#define FU740_PRCI_CLK_HFPCLKPLL 4
-#define FU740_PRCI_CLK_CLTXPLL 5
-#define FU740_PRCI_CLK_TLCLK 6
-#define FU740_PRCI_CLK_PCLK 7
-#define FU740_PRCI_CLK_PCIE_AUX 8
-
-#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
--
2.44.0
