This series add basic support for cv1800b SoC and enable dcache support. The cv1800b utilizes CSR instructions to manipulate the first and second bits in the MHCR register (0x7C1) to indicate the activation status of icache and dcache. As the icache and dcache are already enabled in the FSBL (first stage bootloader) provided by the vendor, and the U-Boot running in S-Mode is unable to manipulate CSR registers, support for operations related to enabling, disabling, or checking the status of the cache is not provided.
Kongyang Liu (2): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 +++++++++ arch/riscv/cpu/cv1800b/Makefile | 7 +++++ arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++ arch/riscv/cpu/cv1800b/cpu.c | 22 ++++++++++++++++ arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++ board/sophgo/milkv_duo/Kconfig | 4 +-- 7 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c -- 2.41.0
