> -----Original Message-----
> From: Marek Vasut <ma...@denx.de>
> Sent: Tuesday, December 19, 2023 5:54 PM
> To: Chee, Tien Fong <tien.fong.c...@intel.com>; Lau, Wan Yee
> <wan.yee....@intel.com>; u-boot@lists.denx.de
> Cc: Simon Glass <s...@chromium.org>; Kever Yang <kever.y...@rock-chips.com>;
> Bin Meng <bmeng...@gmail.com>; Jonas Karlman <jo...@kwiboo.se>; Jean-
> Marie Lemetayer <j.lemeta...@kerlink.fr>; Peng Fan <peng....@nxp.com>;
> Vladimir Zapolskiy <vladimir.zapols...@linaro.org>; Konrad Dybcio
> <konrad.dyb...@linaro.org>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Hea, Kok Kiang
> <kok.kiang....@intel.com>; Maniyam, Dinesh <dinesh.mani...@intel.com>;
> Ng, Boon Khai <boon.khai...@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yusla...@intel.com>; Chong, Teik Heng
> <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.za...@intel.com>; Lim, Jit Loon
> <jit.loon....@intel.com>; Tang, Sieu Mun <sieu.mun.t...@intel.com>
> Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
> SoCFPGA
>
> On 12/19/23 08:03, Chee, Tien Fong wrote:
> > Hi,
> >
> >> -----Original Message-----
> >> From: Lau, Wan Yee <wan.yee....@intel.com>
> >> Sent: Friday, December 8, 2023 4:37 PM
> >> To: u-boot@lists.denx.de
> >> Cc: Simon Glass <s...@chromium.org>; Kever Yang <kever.yang@rock-
> >> chips.com>; Bin Meng <bmeng...@gmail.com>; Jonas Karlman
> >> <jo...@kwiboo.se>; Jean-Marie Lemetayer <j.lemeta...@kerlink.fr>;
> >> Peng Fan <peng....@nxp.com>; Vladimir Zapolskiy
> >> <vladimir.zapols...@linaro.org>; Konrad Dybcio
> >> <konrad.dyb...@linaro.org>; Marek Vasut <ma...@denx.de>; Simon
> >> Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> >> <tien.fong.c...@intel.com>; Hea, Kok Kiang <kok.kiang....@intel.com>;
> >> Maniyam, Dinesh <dinesh.mani...@intel.com>; Ng, Boon Khai
> >> <boon.khai...@intel.com>; Yuslaimi, Alif Zakuan
> >> <alif.zakuan.yusla...@intel.com>; Chong, Teik Heng
> >> <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat
> >> <muhammad.hazim.izzat.za...@intel.com>; Lim, Jit Loon
> >> <jit.loon....@intel.com>; Tang, Sieu Mun <sieu.mun.t...@intel.com>
> >> Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for
> >> Intel SoCFPGA
> >>
> >> From: Wan Yee Lau <wan.yee....@intel.com>
> >>
> >> This driver can be used to provide user a clean interface and all
> >> register settings are centralized in one place, device tree without
> >> need for hardcoding in the source code.
> >>
> >> Signed-off-by: Wan Yee Lau <wan.yee....@intel.com>
> >> ---
> >> .../misc/socfpga_dtreg.txt | 66 ++++++++++
> >> drivers/misc/Kconfig | 7 ++
> >> drivers/misc/Makefile | 1 +
> >> drivers/misc/socfpga_dtreg.c | 117 ++++++++++++++++++
> >> 4 files changed, 191 insertions(+)
> >> create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> create mode 100644 drivers/misc/socfpga_dtreg.c
> >>
> >> diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> b/doc/device- tree-bindings/misc/socfpga_dtreg.txt
> >> new file mode 100644
> >> index 0000000000..5458103f88
> >> --- /dev/null
> >> +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> @@ -0,0 +1,66 @@
> >> +* Firewall and privilege register settings in device tree
> >> +
> >> +Required properties:
> >> +--------------------
> >> +
> >> +- compatible: should contain "intel,socfpga-dtreg"
> >> +- reg: Physical base address and size of block register.
> >> +- intel,offset-settings: 32-bit offset address of block register,
> >> + followed by 32-bit value settings and
> >> + the masking bits, only masking bit
> >> + set to 1 allows modification.
> >> +
> >> +This driver can be used to provide user a clean interface and all
> >> +register settings are centralized in one place, device tree without
> >> +need for hardcoding in the source code.
> >> +
> >> +General setup would be to set the memory address used by the
> >> +register, followed by the offset-settings containing the 32-bit
> >> +offset address of the block register, then the 32-bit value settings
> >> +and lastly the masking bits.
> >> +
> >> +Example:
> >> +--------
> >> +
> >> +Configuration for multiple dtreg node support in device tree:
> >> +
> >> + socfpga_mainfirewall: socfpga-mainfirewall {
> >> + compatible = "intel,socfpga-dtreg";
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + bootph-all;
> >> +
> >> +
> >> coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
> >> + reg = <0xf7100200 0x00000014>;
> >> + intel,offset-settings =
> >> + /* Disable ocram security at CCU
> >> + for non secure
> >> access */
> >> + <0x0000004 0x8000ffff 0xe007ffff>,
> >> + <0x0000008 0x8000ffff 0xe007ffff>,
> >> + <0x000000c 0x8000ffff 0xe007ffff>,
> >> + <0x0000010 0x8000ffff 0xe007ffff>;
> >> + bootph-all;
> >> + };
> >> + };
> >> +
> >> + socfpga_mpfefirewall: socfpga-mpfefirewall {
> >> + compatible = "intel,socfpga-dtreg";
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + bootph-all;
> >> +
> >> + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
> >> + reg = <0xf8020000 0x0000001c>;
> >> + intel,offset-settings =
> >> + /* Disable MPFE firewall for SMMU
> >> */
> >> + <0x00000000 0x00010101
> >> 0x00010101>,
> >> + /* Disable MPFE firewall for HMC
> >> adapter */
> >> + <0x00000004 0x00000001
> >> 0x00010101>;
> >> + bootph-all;
> >> + };
> >> + };
> >> +
> >> +To call the nodes use:
> >> +
> >> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> >> mainfirewall", &dev);
> >> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> >> mpfefirewall",
> >> +&dev);
> >> +
> >> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> >> fccd9b89b8..c423905ba2 100644
> >> --- a/drivers/misc/Kconfig
> >> +++ b/drivers/misc/Kconfig
> >> @@ -683,4 +683,11 @@ config SL28CPLD
> >> the base driver which provides common access methods for the
> >> sub-drivers.
> >>
> >> +config SPL_SOCFPGA_DT_REG
> >> + bool "Enable register setting from device tree in SPL"
> >> + depends on SPL
> >> + help
> >> + Enable register setting from device tree. This also
> >> + provides user a clean interface and all register settings are
> >> + centralized in one place, device tree.
> >> endmenu
> >> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> >> b67b82358a..8f813edd84 100644
> >> --- a/drivers/misc/Makefile
> >> +++ b/drivers/misc/Makefile
> >> @@ -89,3 +89,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
> >> obj-$(CONFIG_ESM_K3) += k3_esm.o
> >> obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
> >> obj-$(CONFIG_SL28CPLD) += sl28cpld.o
> >> +obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o
> >> diff --git a/drivers/misc/socfpga_dtreg.c
> >> b/drivers/misc/socfpga_dtreg.c new file mode 100644 index
> >> 0000000000..982f9592cb
> >> --- /dev/null
> >> +++ b/drivers/misc/socfpga_dtreg.c
> >> @@ -0,0 +1,117 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2023 Intel Corporation <www.intel.com> */
> >> +
> >> +#include <asm/io.h>
> >> +#include <common.h>
> >> +#include <dm.h>
> >> +#include <errno.h>
> >
> > Please move <asm/io.h> above to here
> >
> >> +#include <linux/sizes.h>
>
> A good starting point would be to have socfpga 64bit maintainer , without
> that ,
> these patches are only being archived .
Hi,
Is only one socfpga 64bit maintainer needed or the whole socfpga 64bit
maintainer need to be included for this driver?
Thanks.
Regards,
Wan Yee
