From: Ashok Reddy Soma <ashok.reddy.s...@amd.com> Enable ECO bit for Versal for frequencies above 120Mhz for octal spi to work properly.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.s...@amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com> --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 73ef44fc1c..4906b9ef96 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -55,6 +55,7 @@ #define CQSPI_READ_ID_LEN 3 #define CQSPI_READID_LOOP_MAX 10 #define TERA_MACRO 1000000000000l +#define TAP_GRAN_SEL_MIN_FREQ 120000000 #define OSPI_CTRL_RST 0xF1260304 diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 052d7a1766..43dc4c6e70 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -382,6 +382,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) writel(reg, priv->regbase + CQSPI_REG_CONFIG); + if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + priv->ref_clk_hz >= TAP_GRAN_SEL_MIN_FREQ) + writel(1, priv->regbase + CQSPI_REG_ECO); + cadence_qspi_apb_controller_enable(priv->regbase); } -- 2.27.0