On 02/28/2011 03:57 PM, Xiangfu Liu wrote:
> arch/mips/cpu/xburst/Makefile | 50 +++
> arch/mips/cpu/xburst/config.mk | 33 ++
> arch/mips/cpu/xburst/cpu.c | 160 ++++++++
> arch/mips/cpu/xburst/jz4740.c | 264 ++++++++++++
> arch/mips/cpu/xburst/jz_serial.c | 114 +++++
> arch/mips/cpu/xburst/start.S | 160 ++++++++
> arch/mips/cpu/xburst/start_spl.S | 63 +++
> arch/mips/cpu/xburst/timer.c | 167 ++++++++
> arch/mips/cpu/xburst/usbboot.S | 841
> ++++++++++++++++++++++++++++++++++++++
> 9 files changed, 1852 insertions(+), 0 deletions(-)
> create mode 100644 arch/mips/cpu/xburst/Makefile
> create mode 100644 arch/mips/cpu/xburst/config.mk
> create mode 100644 arch/mips/cpu/xburst/cpu.c
> create mode 100644 arch/mips/cpu/xburst/jz4740.c
> create mode 100644 arch/mips/cpu/xburst/jz_serial.c
> create mode 100644 arch/mips/cpu/xburst/start.S
> create mode 100644 arch/mips/cpu/xburst/start_spl.S
> create mode 100644 arch/mips/cpu/xburst/timer.c
> create mode 100644 arch/mips/cpu/xburst/usbboot.S
Please pay more attention to coding style issues.
- Comments with multiple lines
- Trailing whitespaces
- Inconsistent tab and space usages
- Follow the basic Linux CodingStyle guide
and so on.
Here's quick fixes on 1/7 part. 2/7..7/7 should be checked as well.
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index a9a6e77..6d6ffb7 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -26,8 +26,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
START = start.o
-SOBJS-y =
-COBJS-y = cpu.o timer.o jz_serial.o
+SOBJS-y =
+COBJS-y = cpu.o timer.o jz_serial.o
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index 5eb047d..43e8c3d 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -40,7 +40,7 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
-#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
+#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
void __attribute__((weak)) _machine_restart(void)
{
@@ -79,7 +79,7 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
- for (;addr <= aend;addr += lsize) {
+ for (;addr <= aend; addr += lsize) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
}
@@ -91,7 +91,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
- for (;addr <= aend;addr += lsize)
+ for (;addr <= aend; addr += lsize)
cache_op(Hit_Writeback_Inv_D, addr);
}
@@ -101,7 +101,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
- for (;addr <= aend;addr += lsize)
+ for (;addr <= aend; addr += lsize)
cache_op(Hit_Invalidate_D, addr);
}
@@ -145,7 +145,7 @@ void flush_dcache_all(void)
{
u32 addr;
- for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
+ for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
cache_op(Index_Writeback_Inv_D, addr);
}
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index aedee52..63952b7 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -27,18 +27,19 @@ void enable_interrupts(void)
{
}
-int disable_interrupts(void)
+int disable_interrupts(void)
{
return 0;
}
-/* PLL output clock = EXTAL * NF / (NR * NO)
+/*
+ * PLL output clock = EXTAL * NF / (NR * NO)
* NF = FD + 2, NR = RD + 2
* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
*/
void pll_init(void)
{
- struct jz4740_cpm * cpm = (struct jz4740_cpm *) JZ4740_CPM_BASE;
+ struct jz4740_cpm *cpm = (struct jz4740_cpm *) JZ4740_CPM_BASE;
register unsigned int cfcr, plcr1;
int n2FR[33] = {
@@ -56,7 +57,7 @@ void pll_init(void)
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
- pllout2 = (cfcr & CPM_CPCCR_PCS) ?
+ pllout2 = (cfcr & CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
/* Init USB Host clock, pllout2 must be n*48MHz */
@@ -65,9 +66,9 @@ void pll_init(void)
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
- (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
- CPM_CPPCR_PLLEN; /* enable PLL */
+ (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
+ (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+ CPM_CPPCR_PLLEN; /* enable PLL */
/* init PLL */
writel(cfcr, &cpm->cpccr);
@@ -77,7 +78,7 @@ void pll_init(void)
void sdram_init(void)
{
- struct jz4740_emc * emc = (struct jz4740_emc *) JZ4740_EMC_BASE;
+ struct jz4740_emc *emc = (struct jz4740_emc *) JZ4740_EMC_BASE;
register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
@@ -94,16 +95,15 @@ void sdram_init(void)
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
cpu_clk = CONFIG_SYS_CPU_SPEED;
- mem_clk = cpu_clk *
- div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
+ mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
writel(0, &emc->bcr); /* Disable bus release */
writew(0, &emc->rtcsr); /* Disable clock for counting */
/* Fault DMCR value for mode register setting*/
-#define SDRAM_ROW0 11
-#define SDRAM_COL0 8
-#define SDRAM_BANK40 0
+#define SDRAM_ROW0 11
+#define SDRAM_COL0 8
+#define SDRAM_BANK40 0
dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
@@ -120,41 +120,40 @@ void sdram_init(void)
/* SDRAM timimg */
ns = 1000000000 / mem_clk;
- tmp = SDRAM_TRAS/ns;
- if (tmp < 4)
+ tmp = SDRAM_TRAS / ns;
+ if (tmp < 4)
tmp = 4;
- if (tmp > 11)
+ if (tmp > 11)
tmp = 11;
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
- tmp = SDRAM_RCD/ns;
+ tmp = SDRAM_RCD / ns;
- if (tmp > 3)
+ if (tmp > 3)
tmp = 3;
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
- tmp = SDRAM_TPC/ns;
+ tmp = SDRAM_TPC / ns;
- if (tmp > 7)
+ if (tmp > 7)
tmp = 7;
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
- tmp = SDRAM_TRWL/ns;
+ tmp = SDRAM_TRWL / ns;
- if (tmp > 3)
+ if (tmp > 3)
tmp = 3;
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
- tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
+ tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
- if (tmp > 14)
+ if (tmp > 14)
tmp = 14;
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
/* SDRAM mode value */
- sdmode = EMC_SDMR_BT_SEQ |
+ sdmode = EMC_SDMR_BT_SEQ |
EMC_SDMR_OM_NORMAL |
- EMC_SDMR_BL_4 |
+ EMC_SDMR_BL_4 |
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
- /* Stage 1. Precharge all banks by writing
- * SDMR with DMCR.MRSET=0 */
+ /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
writel(dmcr, &emc->dmcr);
writeb(0, JZ4740_EMC_SDMR0 | sdmode);
@@ -167,8 +166,8 @@ void sdram_init(void)
writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
tmp = SDRAM_TREF / ns;
- tmp = tmp/64 + 1;
- if (tmp > 0xff)
+ tmp = tmp / 64 + 1;
+ if (tmp > 0xff)
tmp = 0xff;
writew(tmp, &emc->rtcor);
writew(0, &emc->rtcnt);
@@ -180,7 +179,7 @@ void sdram_init(void)
while (tmp--)
;
- /* Stage 3. Mode Register Set */
+ /* Stage 3. Mode Register Set */
writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
writeb(0, JZ4740_EMC_SDMR0 | sdmode);
@@ -231,8 +230,7 @@ static void rtc_init(void)
/* U-Boot common routines */
phys_size_t initdram(int board_type)
{
- struct jz4740_emc * emc = (struct jz4740_emc *) JZ4740_EMC_BASE;
-
+ struct jz4740_emc *emc = (struct jz4740_emc *) JZ4740_EMC_BASE;
u32 dmcr;
u32 rows, cols, dw, banks;
ulong size;
diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c
index 65ce993..fa4c5e8 100644
--- a/arch/mips/cpu/xburst/jz_serial.c
+++ b/arch/mips/cpu/xburst/jz_serial.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/jz4740.h>
-
+
/*
* serial_init - initialize a channel
*
@@ -35,7 +35,7 @@
*/
struct jz4740_uart *uart = (struct jz4740_uart *) CONFIG_SYS_UART_BASE;
-int serial_init (void)
+int serial_init(void)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
@@ -48,21 +48,23 @@ int serial_init (void)
/* Set both receiver and transmitter in UART mode (not SIR) */
writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
- /* Set databits, stopbits and parity.
- * (8-bit data, 1 stopbit, no parity) */
+ /*
+ * Set databits, stopbits and parity.
+ * (8-bit data, 1 stopbit, no parity)
+ */
writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
/* Set baud rate */
serial_setbrg();
/* Enable UART unit, enable and clear FIFO */
- writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
+ writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
&uart->iir_fcr);
#endif
return 0;
}
-void serial_setbrg (void)
+void serial_setbrg(void)
{
u32 baud_div, tmp;
@@ -79,18 +81,18 @@ void serial_setbrg (void)
writeb(tmp, &uart->lcr);
}
-int serial_tstc (void)
+int serial_tstc(void)
{
if (readb(&uart->lsr) & UART_LSR_DR)
- return (1);
+ return 1;
return 0;
}
-void serial_putc (const char c)
+void serial_putc(const char c)
{
- if (c == '\n')
- serial_putc ('\r');
+ if (c == '\n')
+ serial_putc('\r');
/* Wait for fifo to shift out some bytes */
while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
@@ -99,7 +101,7 @@ void serial_putc (const char c)
writeb((u8)c, &uart->rbr_thr_dllr);
}
-int serial_getc (void)
+int serial_getc(void)
{
while (!serial_tstc())
;
@@ -107,8 +109,8 @@ int serial_getc (void)
return readb(&uart->rbr_thr_dllr);
}
-void serial_puts (const char *s)
+void serial_puts(const char *s)
{
while (*s)
- serial_putc (*s++);
+ serial_putc(*s++);
}
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index f52e3e8..bbba5c3 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -36,15 +36,15 @@
_start:
/* Initialize GOT pointer */
bal 1f
- nop
+ nop
.word _GLOBAL_OFFSET_TABLE_
1:
- lw gp, 0(ra)
- li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ lw gp, 0(ra)
+ li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la t9, board_init_f
jr t9
- nop
+ nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -85,7 +85,7 @@ relocate_code:
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ addu t1, 4 /* delay slot */
/* If caches were enabled, we would have to flush them here.
* flush d-cache */
@@ -95,7 +95,7 @@ relocate_code:
2:
cache Index_Writeback_Inv_D, 0(t0)
bne t0, t1, 2b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
+ addi t0, CONFIG_SYS_CACHELINE_SIZE
sync
@@ -105,7 +105,7 @@ relocate_code:
3:
cache Index_Invalidate_I, 0(t0)
bne t0, t1, 3b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
+ addi t0, CONFIG_SYS_CACHELINE_SIZE
/* Invalidate BTB */
mfc0 t0, CP0_CONFIG, 7
@@ -120,7 +120,7 @@ relocate_code:
*/
addi t0, a2, in_ram - _start
jr t0
- nop
+ nop
.word uboot_end_data
.word uboot_end
@@ -134,12 +134,12 @@ in_ram:
1:
lw t1, 0(t4)
beqz t1, 2f
- add t1, t6
+ add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
- addi t4, 4 /* delay slot */
+ addi t4, 4 /* delay slot */
/* Clear BSS */
lw t1, -12(t0) /* t1 <-- uboot_end_data */
@@ -150,11 +150,11 @@ in_ram:
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
- sw zero, 0(t1) /* delay slot */
+ sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
jr t9
- move a1, a2 /* delay slot */
+ move a1, a2 /* delay slot */
.end relocate_code
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
index f775e3a..134f79a 100644
--- a/arch/mips/cpu/xburst/start_spl.S
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -21,7 +21,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
+
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
@@ -32,25 +32,27 @@
#include <asm/jz4740.h>
.set noreorder
-
+
.globl _start
.text
_start:
.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
-reset:
- /*
+reset:
+ /*
* STATUS register
* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
*/
li t0, 0x0040FC04
mtc0 t0, CP0_STATUS
- /* CAUSE register
- * IV=1, use the specical interrupt vector (0x200) */
+ /*
+ * CAUSE register
+ * IV=1, use the specical interrupt vector (0x200)
+ */
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
-
+
bal 1f
- nop
+ nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
@@ -59,5 +61,5 @@ reset:
la sp, 0x80004000
la t9, nand_boot
j t9
- nop
+ nop
diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c
index 4472f8e..47d8908 100644
--- a/arch/mips/cpu/xburst/timer.c
+++ b/arch/mips/cpu/xburst/timer.c
@@ -72,7 +72,7 @@ void set_timer(ulong t)
gd->tbl = t;
}
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
{
ulong tmo,tmp;
@@ -121,7 +121,7 @@ ulong get_timer_masked (void)
return gd->tbl;
}
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
diff --git a/arch/mips/cpu/xburst/usbboot.S b/arch/mips/cpu/xburst/usbboot.S
index 97fcbbf..89f995e 100644
--- a/arch/mips/cpu/xburst/usbboot.S
+++ b/arch/mips/cpu/xburst/usbboot.S
@@ -157,7 +157,7 @@ xfer_d2i:
icache_return:
/*
- * User code can return to here after executing itself in
+ * User code can return to here after executing itself in
* icache, by jumping to $31.
*/
b usb_boot_return
@@ -192,7 +192,7 @@ usb_command_loop:
beqz $9, check_intr_ep0in
nop
- /* 1. Handle USB reset interrupt */
+ /* 1. Handle USB reset interrupt */
handle_reset_intr:
lbu $9, 0x01($27) /* read POWER */
andi $9, 0x10 /* test HS_MODE */
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
index e9209f6..c5a5154 100644
--- a/arch/mips/include/asm/jz4740.h
+++ b/arch/mips/include/asm/jz4740.h
@@ -33,7 +33,7 @@
#define JZ4740_IRQ_TCU2 21
#define JZ4740_IRQ_TCU1 22
#define JZ4740_IRQ_TCU0 23
-#define JZ4740_IRQ_UDC 24
+#define JZ4740_IRQ_UDC 24
#define JZ4740_IRQ_GPIO3 25
#define JZ4740_IRQ_GPIO2 26
#define JZ4740_IRQ_GPIO1 27
@@ -68,7 +68,7 @@
#define JZ4740_ETH_BASE 0x13100000
/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
+#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
/* GPIO (General-Purpose I/O Ports) */
/* = 0,1,2,3 */
@@ -342,8 +342,8 @@
#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT 3
-#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
+#define CPM_LCR_DOZE_DUTY_BIT 3
+#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
#define CPM_LCR_DOZE_ON (1 << 2)
#define CPM_LCR_LPM_BIT 0
#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
@@ -1005,7 +1005,7 @@ struct jz4740_wdt {
};
struct jz4740_uart {
- uint8_t rbr_thr_dllr;
+ uint8_t rbr_thr_dllr;
/* 0x00 R 8b receive buffer reg */
/* 0x00 W 8b transmit hold reg */
/* 0x00 RW 8b divisor latch low reg */
@@ -1057,7 +1057,7 @@ struct jz4740_msc {
struct jz4740_emc {
uint32_t bcr; /* 0x00 BCR */
uint32_t pad00[3];
- uint32_t smcr[5];
+ uint32_t smcr[5];
/* x10 Static Memory Control Register 0 */
/* x14 Static Memory Control Register 1 */
/* x18 Static Memory Control Register 2 */
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index a7d16e3..bb6980c 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -38,16 +38,16 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
.eccbytes = 72,
.eccpos = {
12, 13, 14, 15, 16, 17, 18, 19,
- 20, 21, 22, 23, 24, 25, 26, 27,
+ 20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42, 43,
- 44, 45, 46, 47, 48, 49, 50, 51,
- 52, 53, 54, 55, 56, 57, 58, 59,
- 60, 61, 62, 63, 64, 65, 66, 67,
- 68, 69, 70, 71, 72, 73, 74, 75,
+ 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 79, 80, 81, 82, 83},
.oobfree = {
- {.offset = 2,
+ {.offset = 2,
.length = 10},
{.offset = 84,
.length = 44}}
@@ -103,7 +103,7 @@ static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
if (ctrl & NAND_NCE)
- writel(readl(&emc->nfcsr) | EMC_NFCSR_NFCE1,
&emc->nfcsr);
+ writel(readl(&emc->nfcsr) | EMC_NFCSR_NFCE1,
&emc->nfcsr);
else
writel(readl(&emc->nfcsr) & ~EMC_NFCSR_NFCE1,
&emc->nfcsr);
}
@@ -200,7 +200,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
volatile u8 *paraddr = (volatile u8 *) &emc->nfpar[0];
/* Set PAR values */
- static uint8_t all_ff_ecc[] =
+ static uint8_t all_ff_ecc[] =
{0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f};
if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
@@ -244,19 +244,19 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
case 4:
index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
+ mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
EMC_NFERR_MASK_BIT;
jz_rs_correct(dat, index, mask);
case 3:
index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
+ mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
EMC_NFERR_MASK_BIT;
jz_rs_correct(dat, index, mask);
case 2:
- index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
+ index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
+ mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
EMC_NFERR_MASK_BIT;
jz_rs_correct(dat, index, mask);
case 1:
@@ -302,9 +302,9 @@ extern int serial_init(void);
#endif
uint32_t reg;
- reg = readl(&emc->nfcsr);
+ reg = readl(&emc->nfcsr);
reg |= EMC_NFCSR_NFE1; /* EMC setup, Set NFE bit */
- writel(reg, &emc->nfcsr);
+ writel(reg, &emc->nfcsr);
writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
diff --git a/include/configs/nanonote.h b/include/configs/nanonote.h
index e19fe58..4dcc304 100644
--- a/include/configs/nanonote.h
+++ b/include/configs/nanonote.h
@@ -149,7 +149,7 @@
*
*/
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this
addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
/* Start NUB from this addr*/
/*
diff --git a/nand_spl/board/xburst/nanonote/Makefile
b/nand_spl/board/xburst/nanonote/Makefile
index 9775d14..2398430 100644
--- a/nand_spl/board/xburst/nanonote/Makefile
+++ b/nand_spl/board/xburst/nanonote/Makefile
@@ -47,7 +47,7 @@ all: $(obj).depend $(ALL)
#from NAND flash using hardware Reed-Solomon ECC. If no ECC error is detected
or ECC error is
#correctable, the boot program then branches to internal SRAM at 4 bytes
offset. If it detects an
#uncorrectable ECC error, it will continue to read the backup area of data
from NAND flash using
-#hardware Reed-Solomon ECC.
+#hardware Reed-Solomon ECC.
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
cat $< $(nandobj)junk1 > $(nandobj)junk2
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