On Thu, 19 Oct 2023 16:21:54 -0300
Fabio Estevam <feste...@gmail.com> wrote:
> From: Fabio Estevam <feste...@denx.de>
>
> With DM enabled, there is no need for board code to initialize
> the Ethernet interfaces.
>
> The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
> need to enable the RGMII TX clk output.
>
> Also, there is no need for describing the deprecated phy-reset FEC
> properties, nor passing reset properties to the EQOS interface in
> u-boot.dtsi.
>
> Remove all these unneeded pieces.
>
> Tested both Ethernet interfaces after these changes.
>
> Signed-off-by: Fabio Estevam <feste...@denx.de>
Reviewed-by: Hugo Villeneuve <hvillene...@dimonoff.com>
> ---
> Changes since v1:
> - Removed Ethernet related headers. (Hugo)
> - Also removed custom eqos reset properties from u-boot.dtsi.
>
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 14 -------------
> board/freescale/imx8mp_evk/imx8mp_evk.c | 28 +------------------------
> 2 files changed, 1 insertion(+), 41 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 0bf489b46248..51c84383673c 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -137,17 +137,3 @@
> &wdog1 {
> bootph-pre-ram;
> };
> -
> -ðphy0 {
> - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> - reset-delay-us = <15000>;
> - reset-post-delay-us = <100000>;
> -};
> -
> -&fec {
> - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
> - phy-reset-duration = <15>;
> - phy-reset-post-delay = <100>;
> -};
> -
> -
> diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
> b/board/freescale/imx8mp_evk/imx8mp_evk.c
> index a24b8c1d8608..42291c958e39 100644
> --- a/board/freescale/imx8mp_evk/imx8mp_evk.c
> +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
> @@ -7,8 +7,6 @@
> #include <env.h>
> #include <errno.h>
> #include <init.h>
> -#include <miiphy.h>
> -#include <netdev.h>
> #include <linux/delay.h>
> #include <asm/global_data.h>
> #include <asm/mach-imx/iomux-v3.h>
> @@ -20,33 +18,9 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static void setup_fec(void)
> -{
> - struct iomuxc_gpr_base_regs *gpr =
> - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> -
> - /* Enable RGMII TX clk output */
> - setbits_le32(&gpr->gpr[1], BIT(22));
> -}
> -
> -#if CONFIG_IS_ENABLED(NET)
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> - return 0;
> -}
> -#endif
> -
> int board_init(void)
> {
> - int ret = 0;
> -
> - if (IS_ENABLED(CONFIG_FEC_MXC)) {
> - setup_fec();
> - }
> -
> - return ret;
> + return 0;
> }
>
> int board_late_init(void)
> --
> 2.34.1
>
>
