On 10/1/23 16:52, Andre Przywara wrote:
As the code to switch an ARM core from secure to the non-secure state
needs to know the base address of the Generic Interrupt Controller
(GIC), we read an Arm Cortex defined system register that is supposed to
hold that base address. However there are SoCs out there that get this
wrong, and this CBAR register either reads as 0 or points to the wrong
address. To accommodate those systems, so far we use a macro defined in
some platform specific header files, for affected boards.
To simplify future extensions, replace that macro with a Kconfig variable
that holds this override address, and define a default value for SoCs
that need it.
Hi Andre,
Looks great to me. I'll update my PSCI series atop this once either this
or the R528 series lands (I don't want my series to depend on *two*
pending patchsets).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Sam Edwards <cfswo...@gmail.com>
Cheers,
Sam
