On 9/29/23 13:34, Anatolij Gustschin wrote:
> Add USART1 clock parents and mux configuration. This allows
> support for configuring the USART1 as the serial console in
> SPL and U-Boot via device tree. Without this patch the SPL
> with usart1 serial console enabled crashes because it can
> not find the clock specified in the device tree for usart1.
>
> Signed-off-by: Anatolij Gustschin <ag...@denx.de>
> ---
> drivers/clk/stm32/clk-stm32mp1.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/stm32/clk-stm32mp1.c
> b/drivers/clk/stm32/clk-stm32mp1.c
> index 6150287694..f3ac8c7583 100644
> --- a/drivers/clk/stm32/clk-stm32mp1.c
> +++ b/drivers/clk/stm32/clk-stm32mp1.c
> @@ -72,6 +72,7 @@ DECLARE_GLOBAL_DATA_PTR;
> #define RCC_PLL2CSGR 0xA4
> #define RCC_I2C46CKSELR 0xC0
> #define RCC_SPI6CKSELR 0xC4
> +#define RCC_UART1CKSELR 0xC8
> #define RCC_CPERCKSELR 0xD0
> #define RCC_STGENCKSELR 0xD4
> #define RCC_DDRITFCR 0xD8
> @@ -317,6 +318,7 @@ enum stm32mp1_parent_sel {
> _SPI45_SEL,
> _SPI6_SEL,
> _RTC_SEL,
> + _UART1_SEL,
> _PARENT_SEL_NB,
> _UNKNOWN_SEL = 0xff,
> };
> @@ -557,6 +559,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[]
> = {
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
> + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
> @@ -602,6 +605,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[]
> = {
> static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
> static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
> static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
> +static const u8 uart1_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER,
> + _PLL4_Q, _HSE_KER};
> static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
> _HSE_KER};
> static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
> @@ -659,6 +664,7 @@ static const struct stm32mp1_clk_sel
> stm32mp1_clk_sel[_PARENT_SEL_NB] = {
> STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
> (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
> rtc_parents),
> + STM32MP1_CLK_PARENT(_UART1_SEL, RCC_UART1CKSELR, 0, 0x7, uart1_parents),
> };
>
> #ifdef STM32MP1_CLOCK_TREE_INIT
> @@ -786,6 +792,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB]
> = {
> [_SPI1_SEL] = "SPI1",
> [_SPI45_SEL] = "SPI45",
> [_RTC_SEL] = "RTC",
> + [_UART1_SEL] = "UART1",
> };
>
> static const struct stm32mp1_clk_data stm32mp1_data = {
Hi Anatolij
Reviewed-by: Patrice Chotard <patrice.chot...@foss.st.com>
Thanks
Patrice
