From: Poonam Aggrwal <poonam.aggr...@freescale.com> Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum.
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com> Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b657ab2..ddbfca9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -91,6 +91,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -125,6 +129,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1015 is single core version of P1024 */ #elif defined(CONFIG_P1015) -- 1.7.2.3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
