Baidu,
> > > 2011/3/5 Andre Schwarz <andre.schw...@matrix-vision.de > [mailto:andre.schw...@matrix-vision.de] > > > > All, > > > > sorry to bother you again. > > After my harddisk died I'm porting my latest 8377 work to TOT. > > Unfortunately I'm lacking some commits that haven't been pushed to backup. > > > > > > But everything's fine so far and the system is up and running, except PCIe. > > > > Using the "old" binary left on the server PCIe has been working fine : > > > > U-Boot 2010.12-rc1-00596-gcef659f-dirty (Nov 22 2010 - 17:22:20) MPC83XX > > ... > > PCIE1: link > > > > and the Wifi card is present and usable by Linux. > > > > => pci 2 > > Scanning PCI devices on bus 2 > > BusDevFun VendorId DeviceId Device Class Sub-Class > > _____________________________________________________________ > > 02.00.00 0x168c 0x001c Network controller 0x00 > > > > > > > > With latest code running on the *same piece of hardware* > > > > U-Boot 2011.03-rc1-00129-g1ce1ed1-dirty (Mar 04 2011 - 16:31:40) MPC83XX > > > > I get "PCIE1: No link" > > > > > > Dumping SerDes (e3000 + e3100) and PCIe core (400-7ff) registers shows > > now difference between both versions. > > > > Any ideas what might be responsible for the link not being established ? > > > > > > the link is the physical status of the pcie. hmm - that's clear. I'm running the very same pci_init code, i.e. fsl_setup_serde and the resulting register setting (PCIe *and* SerDes) are identical. > So please to check the setting about the pcie. Such as x1/x2，clock，serdes > setting in functiono pci_init_board(). What exactly do you mean with x1/x2 clock ? Are you talking about PCIe link width ? It's 2 times x1 with 100MHz external refclk and internal PCIe clocks matches CSB clock 333MHz. Regards, André MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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