Hi Kever and Steven,
On 2023-08-12 04:50, Kever Yang wrote:
> Add Steven Liu,
>
> Hi Steven,
>
> Please help to review this patch.
>
>
> On 2023/8/4 01:44, Jonas Karlman wrote:
>> rk3568_set_drive configures a second reg for specific pins. Mainline
>> linux does not do this and vendor U-Boot only run similar code when bit
>> 14 and 15 are both 0 in PMU_GRF_SOC_CON0.
>
> The base version of this driver also based on vendor U-Boot, right? But
> this part of
>
> logic is different? interesting...
Yes, this seemed strange.
I have sent a v2 of this patch that restore part of this code after
looking closer in Hardware Design Guide, PinOut and TRM documents.
If I understand correctly the first reg should contain DS[5:0] and the
second reg should contain DS[11:6], not a copy of DS[5:0].
Regards,
Jonas
>
>
> Thanks,
>
> - Kever
>
>> Something that presumably only
>> early revisions of the SoC have, all my RK3566/RK3568 boards read back
>> bit 15 as 1, even on boards dated back to 21H1.
>>
>> This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
>> drive is configured according to the device tree.
>>
>> Input schmitt is configured in 2-bit fields on RK3568 compared to earlier
>> generation and 2'b10 should be used to enable input schmitt.
>>
>> Remove the code that presumably was intended for early pre-production
>> revisions of the SoC and write correct values for input schmitt setting.
>> Also change to use regmap_update_bits to closer match linux driver.
>>
>> Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver")
>> Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
>> ---
>> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 52 ++++++-----------------
>> 1 file changed, 14 insertions(+), 38 deletions(-)
>>
[...]
