The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.
This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Patrice Chotard <patrice.chot...@foss.st.com>
Cc: Patrick Delaunay <patrick.delau...@foss.st.com>
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/mach-stm32mp/psci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 50e3fc4ae45..79734b5289b 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -754,7 +754,7 @@ void __secure psci_system_suspend(u32 __always_unused
function_id,
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
- PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
+ PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
--
2.40.1
