To align with kernel and remove duplication rearrange boothm node. Signed-off-by: Udit Kumar <u-kum...@ti.com> --- .../k3-j7200-common-proc-board-u-boot.dtsi | 45 ------------------- arch/arm/dts/k3-j7200-common-proc-board.dts | 3 ++ arch/arm/dts/k3-j7200-main.dtsi | 3 ++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 2 + arch/arm/dts/k3-j7200-som-p0.dtsi | 1 + 5 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index e5ae8f44ed..fa3baf242b 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -3,14 +3,6 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ -&cbass_main { - bootph-pre-ram; -}; - -&main_navss { - bootph-pre-ram; -}; - &cbass_mcu_wakeup { bootph-pre-ram; @@ -62,10 +54,6 @@ }; }; -&secure_proxy_main { - bootph-pre-ram; -}; - &dmsc { bootph-pre-ram; k3_sysreset: sysreset-controller { @@ -86,22 +74,6 @@ bootph-pre-ram; }; -&wkup_pmx0 { - bootph-pre-ram; -}; - -&main_pmx0 { - bootph-pre-ram; -}; - -&main_uart0 { - bootph-pre-ram; -}; - -&mcu_uart0 { - bootph-pre-ram; -}; - &main_sdhci0 { bootph-pre-ram; }; @@ -129,19 +101,6 @@ bootph-pre-ram; }; -&mcu_fss0_hpb0_pins_default { - bootph-pre-ram; -}; - -&fss { - bootph-pre-ram; -}; - - -&hbmc_mux { - bootph-pre-ram; -}; - &serdes_ln_ctrl { u-boot,mux-autoprobe; }; @@ -150,10 +109,6 @@ u-boot,mux-autoprobe; }; -&serdes0 { - bootph-pre-ram; -}; - &main_r5fss0 { ti,cluster-mode = <0>; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 77f9922260..9e6edecbde 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -183,6 +183,7 @@ }; &mcu_uart0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; @@ -190,6 +191,7 @@ }; &main_uart0 { + bootph-pre-ram; status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; @@ -338,6 +340,7 @@ }; &serdes0 { + bootph-pre-ram; serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index fb9e4842c1..3dfbeca4ef 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -13,6 +13,7 @@ }; &cbass_main { + bootph-pre-ram; msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x100000>; @@ -84,6 +85,7 @@ }; main_navss: bus@30000000 { + bootph-pre-ram; compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -119,6 +121,7 @@ }; secure_proxy_main: mailbox@32c00000 { + bootph-pre-ram; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 7ed6c31c7c..e302c3d6ac 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -454,6 +454,7 @@ }; fss: syscon@47000000 { + bootph-pre-ram; compatible = "syscon", "simple-mfd"; reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; @@ -461,6 +462,7 @@ ranges; hbmc_mux: hbmc-mux { + bootph-pre-ram; compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4 0x2>; /* HBMC select */ diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi index 7776f2d0ba..db1d749b52 100644 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi @@ -84,6 +84,7 @@ &wkup_pmx0 { mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ -- 2.34.1
