Hi David, On Friday 28 January 2011 14:57:06 David Thomas wrote: > We have a board with an AMCC PPC 405EX connected to two fpga's with PCIE > interfaces. > > On some boards, on power up, the u-boot code hangs in the while loop in > the following code waiting for PCIE1 to come out of reset. PCIE0 comes > out of reset successfully. > > The PHYSTA for PCIE1 always reads back with the value 0x30000000, > indicating the the interface is in the P2 state and that the PLL has not > locked. > > If a timeout is added and U-boot is allowed to proceed, a machine check > is eventually taken and the processor reboots. During the reboot, u-boot > runs through the same code but this time both PCIE interfaces > successfully come out of reset and the board comes up normally. > > Any suggestions about what might be happening here?
Did you try setting the "pcidelay" environment variable. This will delay initializing the PCI(e) interfaces for n milliseconds. Try setting it to 3000 (3 seconds) to see if this helps. Please note that you need to set CONFIG_PCI_BOOTDELAY in your board config header to enable this "feature". Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
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