Hi Michael,
Le 29/01/2011 02:00, Michael Spang a écrit :
> This code intends to read the SDRAM controller base address registers
> but is instead reading the CPU window base address registers.
Side note: IIUC this change is not required since the CPU Window
registers match the SDRAM controller registers on orion5x in U-boot; but
it is fine if only for the sake of correctness, and assuming it works
for other orion5x boards (testing underway for edminiv2).
> Signed-off-by: Michael Spang<msp...@csclub.uwaterloo.ca>
> ---
> arch/arm/cpu/arm926ejs/orion5x/dram.c | 2 +-
> arch/arm/include/asm/arch-orion5x/orion5x.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c
> b/arch/arm/cpu/arm926ejs/orion5x/dram.c
> index b749282..7f3a318 100644
> --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
> +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
> @@ -38,7 +38,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank)
> {
> struct orion5x_ddr_addr_decode_registers *winregs =
> (struct orion5x_ddr_addr_decode_registers *)
Please remove the 'ddr_' part of the struct name while you're at it:
this struct is not DDR specific, it also covers CPU window register.
> - ORION5X_CPU_WIN_BASE;
> + ORION5X_SDRAM_CTRL_BASE;
>
> u32 result = 0;
> u32 enable = 0x01& winregs[bank].size;
> diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h
> b/arch/arm/include/asm/arch-orion5x/orion5x.h
> index e3d3f76..f262ad1 100644
> --- a/arch/arm/include/asm/arch-orion5x/orion5x.h
> +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
> @@ -42,6 +42,7 @@
> #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
>
> /* Documented registers */
> +#define ORION5X_SDRAM_CTRL_BASE
> (ORION5X_REGISTER(0x01500))
> #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
> #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
> #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
Amicalement,
--
Albert.
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