Ok, I'm updated my u-boot source code to the v2010.12 release and i'm
still seeing the same behaviour as with the earlier version...
in summary:
early in the boot process, in the start.S file, the L1 DCache is
configured for use as some initial RAM, the stack is located there, and
the global data structure, gd_t, is located there... when I debug my
u-boot build i can set breakpoints, e.g. in cpu_init_f, and the
breakpoint is hit and I can single step thru the code, but when the
return from the function is executed i get the 'Cannot access memory at
address..." error, but apparently the call does return, because I can
single step on to the next function that is call, board_init_f...
Additionally, if I set a breakpoint in board_init_f, after the
statement that initializes the gd_t pointer variable 'gd', and then try
to print the structure or just examine the memory locations i get the
same "Cannot access memory at address..." error...
so i'm assuming gdb working with a bdi3000 should be able to access this
L1Dcache when configured to be used as this initial RAM area for u-boot,
is this assumption correct?
the code in start.S is coded to be common for all mpc85xx boards (its in
the arch/powerpc/cpu/mpc85xx directory) with some config options from
the board specific <board>_config.h file.
My board is custom but modeled after the MPC8548CDS and at least at this
point of execution I think components common to any MPC8548 board are
being set up... I left the #define that specifies the address for this
initial RAM unchanged, 0xe4010000 ( i had changed it to 0xd8010000 when
i was using 1.3.4, but could see a reason that was required...)
could my bdi3000 config file affect this in any way? i've attached it
for reference...
my thanks for your time and any ideas or suggestions are greatly
appreciated...
davis mcpherson
On 01/22/2011 12:39 PM, Wolfgang Denk wrote:
Dear davis mcpherson,
In message<4d3b0525.4080...@gmail.com> you wrote:
I'm trying to get u-boot version 1.3.4 working a custom MPC8548 based
board (version 1.1.4 currently works fine on this board so the hardware
is known to be good). I'm encountering the following problem during the
Sorry, but I don't even continue reading. v1.3.4 is 2.5 years old,
i. e. hopelessly obsolete. Any efforts on this old stuff are only a
waste of time.
Do yourself (and us) a favour and use current code instead (at least
v2010.12, or bettter current top of tree from the git repository).
Best regards,
Wolfgang Denk
;bdiGDB configuration file for CDS8548 Rev.2 silicon
;---------------------------------------------------
;
; This setup is used to program the CDS8548 flash
;
[INIT]
;
;================= setup TLB entries =========================
; Move the L2SRAM to the initial MMU page
WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error
WM32 0xFF720000 0x60010000 ;L2CTL
WM32 0xFF720100 0xFFF80000 ;L2SRBAR0 (rev.2): map to 0x0_FFF80000
WM32 0xFF720104 0x00000000 ;L2SRBAREA0 (Rev.2)
WM32 0xFF720000 0xA0010000 ;L2CTL
;
; load and execute some boot code (necessary for STARTUP HALT)
;WM32 0xfffffffc 0x48000000 ;loop
;EXEC 0xfffffffc
;
; load TLB entries, helper code @ 0xfffff000
WM32 0xfffff000 0x7c0007a4 ;tlbwe
WM32 0xfffff004 0x7c0004ac ;msync
WM32 0xfffff008 0x48000000 ;loop
WSPR 628 0x00000000 ;MAS4:
WSPR 630 0x00000000 ;MAS7:
;
; 64 MB TLB1 #1 0xe0000000 - 0xe3ffffff
WSPR 624 0x10010000 ;MAS0:
WSPR 625 0x80000800 ;MAS1:
WSPR 626 0xe000000a ;MAS2:
WSPR 627 0xe0000015 ;MAS3:
EXEC 0xfffff000
;
; 16 MB TLB1 #2 0xff000000 - 0xffffffff
WSPR 624 0x10020000 ;MAS0:
WSPR 625 0x80000700 ;MAS1:
WSPR 626 0xff00000a ;MAS2:
WSPR 627 0xff000015 ;MAS3:
EXEC 0xfffff000
;
; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff
WSPR 624 0x10000000 ;MAS0:
WSPR 625 0x80000700 ;MAS1:
WSPR 626 0xf0000008 ;MAS2:
WSPR 627 0xf0000015 ;MAS3:
EXEC 0xfffff000
;
; Remove the L2SRAM from the initial MMU page
WM32 0xFF720000 0x20010000 ;L2CTL
WM32 0xFF720000 0x20000000 ;L2CTL
;================= end setup TLB entries =====================
;
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000
;
; Initialize LAWBARs
WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000
WM32 0xe0000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB
WM32 0xe0000C28 0x000e0000 ;LAWBAR1 : @0xe0000000
WM32 0xe0000C30 0x8040001d ;LAWAR1 : Local Bus 1GB
;
; Setup Flash chip select
WM32 0xe0005000 0xf8001001 ;BR0
WM32 0xe0005004 0xf8006e65 ;OR0
WM32 0xe0005008 0xf0001001 ;BR1
WM32 0xe000500C 0xff806e65 ;OR1
;
; Set GPIO for flash Write Protect
;
WM32 0xe00e0030 0x00000200 ; FLASH WP GPOUT27
WM32 0xe00e0040 0x00000010 ; FLASH WP GPOUT27
;
; Setup flash programming workspace in L2SRAM
;WM32 0xe0020e44 0x0000001c ;L2ERRDIS: disable parity error
;WM32 0xe0020000 0x60010000 ;L2CTL
;WM32 0xe0020100 0xf0000000 ;L2SRBAR0 (Rev.2): map to 0x0_F0000000
;WM32 0xe0020104 0x00000000 ;L2SRBAREA0 (Rev.2)
;WM32 0xe0020000 0xa0010000 ;L2CTL
;WSPR 63 0xf0000000 ;IVPR to workspace
;WSPR 415 0x0001500 ;IVOR15 : Debug exception
;WM32 0xf0001500 0x48000000 ;write valid instruction
;
;================= end setup for flash programming ===========
;
[TARGET]
CPUTYPE 8548 ;the CPU type
REGLIST E500 ; send register list in e500 mode
JTAGCLOCK 1 ;use 16 MHz JTAG clock
;STARTUP LOOP ;use boot loop in L2SRAM
STARTUP HALT ;halt core while HRESET is asserted
BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP 2000 ;give reset time to complete
POWERUP 5000 ;start delay after power-up detected in ms
SIO 7 115200 ;jsr
;MMU XLAT
;PTBASE 0x000000f0
[HOST]
IP 192.168.65.51
FILE o3b.elf
FORMAT BIN
LOAD MANUAL ;load code MANUAL or AUTO after reset
DUMP /Leapfrog/tftpboot/o3b_e500.bin
PROMPT cpb-o3b>
[FLASH]
CHIPTYPE MIRRORX16 ;AM29LV641D
CHIPSIZE 0x8000000 ;The size of one flash chip in bytes
BUSWIDTH 16 ;The width of the flash memory bus in bits (8 |
16 | 32)
;WORKSPACE 0x00000000 ;workspace in DDR SDRAM
;FILE /adsp1/jr001950/u-boot.bin
FORMAT BIN 0xFFF80000
[REGS]
FILE $reg8548.def
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