> -----Original Message----- > From: Fabio Estevam <feste...@gmail.com> > Sent: 2023年1月24日 3:34 > To: Peng Fan (OSS) <peng....@oss.nxp.com> > Cc: sba...@denx.de; dl-uboot-imx <uboot-...@nxp.com>; u- > b...@lists.denx.de; Peng Fan <peng....@nxp.com> > Subject: Re: [PATCH 41/41] imx9: support i.MX93 9x9 QSB board > > Hi > > On Mon, Jan 23, 2023 at 5:30 AM Peng Fan (OSS) <peng....@oss.nxp.com> > wrote: > > > > From: Peng Fan <peng....@nxp.com> > > > > Support i.MX93 9x9 Quick Start Board, UART/SD/MMC/I2C supported. > > > > Boot Log as below: > > U-Boot SPL 2023.01-rc3-00069-g7c3dea52355-dirty (Dec 14 2022 - > > 11:46:43 +0800) > > SOC: 0xa0009300 > > LC: 0x40010 > > M33 prepare ok > > The last three lines above are too noisy. Please move them to debug level. [Peng Fan] Ok
> > > Normal Boot > > Trying to boot from BOOTROM > > Boot Stage: Primary boot > > image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from > > 0x42000 by ROM_API > > NOTICE: BL31: v2.6(release):v2.6-277-g5234dfb98 > > NOTICE: BL31: Built : 10:11:35, Dec 9 2022 > > > > U-Boot 2023.01-rc3-00069-g7c3dea52355-dirty (Dec 14 2022 - 11:46:43 > > +0800) > > > > CPU: i.MX93(52) rev1.0 1700 MHz (running at 1692 MHz) > > CPU: Consumer temperature grade (0C to 95C) at 33C > > Reset cause: POR (0x1) > > Model: NXP i.MX93 9x9 Quick Start Board > > DRAM: 2 GiB > > Core: 51 devices, 18 uclasses, devicetree: separate > > MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 > > Loading Environment from MMC... OK > > In: serial@44380000 > > Out: serial@44380000 > > Err: serial@44380000 > > > > BuildInfo: > > - ELE firmware version 0.0.8-80d3db4b > > What does ELE firmware mean? > > Please add a doc/board/nxp/imx93_qsb.rst with instructions on how to > build U-Boot + all required firmware for this board. [Peng Fan] Sure. > > > +/* Link Definitions */ > > + > > +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 > > +#define CFG_SYS_INIT_RAM_SIZE 0x200000 > > + > > +#define CFG_SYS_SDRAM_BASE 0x80000000 > > +#define PHYS_SDRAM 0x80000000 > > +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > > + > > +/* Using ULP WDOG for reset */ > > +#define WDOG_BASE_ADDR WDG3_BASE_ADDR > > This should be retrieved from the device tree. [Peng Fan] Ok. If no other major comments, I will post out V2 in a few days. Thanks, Peng.
