On Tue, 10 Jan 2023 at 13:57, Fabio Estevam <feste...@gmail.com> wrote: > > > For this we're waiting for Transmitter Complete bit, indicating > > that the FIFO and the shift register are empty. > > > > flushing has a 4ms timeout guard, which is normally more than > > enough to consume the FIFO @ low baudrate (9600bps). > > > > Signed-off-by: Loic Poulain <loic.poul...@linaro.org> > > --- > > v2: Add this commit to the series > > Should this patch come first in the series? > > In case someone is bisecting, the current patch 1/2 may cause serial > corruption, > which is fixed by 2/2. > > Can we avoid corruption by swapping the order of these patches?
Indeed, sending a v3. Thanks, Loic
