From: Takahiro Kuwano <takahiro.kuw...@infineon.com>
CFR5V[6] is reserved bit and must always be 1.
Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Signed-off-by: Takahiro Kuwano <takahiro.kuw...@infineon.com>
---
include/linux/mtd/spi-nor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 30f15452aa68..181eb6710d7e 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -194,7 +194,7 @@
#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
#define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */
#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x43
#define SPINOR_OP_CYPRESS_RD_FAST 0xee
/* Supported SPI protocols */
--
2.25.1
