On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
From: Fabien Parent <fpar...@baylibre.com>
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul....@mediatek.com>
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 317
+++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
6 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
[deleted]
+ u3phy0: usb-phy@11f40000 {
change node name as t-phy as u3phy3?
Got it, will fix it in next version.
+ compatible = "mediatek,generic-tphy-v2";
prefer to add "mediatek,mt8195-tphy" before generic's
Will fix it in next version.
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&clk26m>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
these two clocks are optional, if sw can't control it, no need add it
here.
MediaTek's clock driver developer will upstream clock driver when
refactoring
work has been completed. Before clock driver is applied to trunk, we can use
clk26m only.
Will fix it in next version.
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&clk26m>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
ditto
Will fix it in next version.
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@11200000 {
+ compatible ="mediatek,mt8195-mtu3",
"mediatek,mtu3";
+ reg = <0 0x11200000 0 0x3e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
"mac" can be removed, the driver get it from the first child node
Will fix it in next version.
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 128
IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ xhci0: xhci@11200000 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129
IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck",
"ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,generic-tphy-v2";
add specific one
Will fix it in next version.
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "okay";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci3: xhci3@112b0000 {
change node name as xhci? prefer to use the same name
Since there are other board manufacturers will use the
other HOST ports, like xhci1 or xhci2 with USB mass storage
function by their needs.
I'll add these 2 node in dtsi in next version.
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
remove "mac"
Will fix it in next version.
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
mediatek/Kconfig
index 04aa2fd97f..3a2af1cdee 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -67,6 +67,15 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
LPDDR3
and LPDDR4 options.
+config TARGET_MT8195
+ bool "MediaTek MT8195 SoC"
+ select ARM64
+ help
+ The MediaTek MT8195 is a ARM64-based SoC with a quad-core
Cortex-A73 and
+ a quad-core Cortex-A53. It is including UART, SPI, USB3.0
device and hosts,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
LPDDR3
+ and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
TARGET_MT8183 || TARGET_MT8195
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 ||
TARGET_MT7986
default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-
mediatek/Makefile
index fc85293f71..fbbb5431d1 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-
mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-
mediatek/mt8195/init.c
new file mode 100644
index 0000000000..1eb4ade6c5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/init.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Macpaul Lin <macpaul....@mediatek.com>
+ * Author: Fabien Parent <fpar...@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8195\n");
+ return 0;
+}
+
+static struct mm_region mt8195_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8195_mem_map;
Thanks a lot!
Macpaul Lin
