On Tue, Jan 04, 2011 at 04:08:29PM -0600, Scott Wood wrote:
> On Mon, Dec 27, 2010 at 05:47:01PM -0700, John Rigby wrote:
> > diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
> > index 76b8566..1ae2cd0 100644
> > --- a/nand_spl/nand_boot.c
> > +++ b/nand_spl/nand_boot.c
> > @@ -27,6 +27,15 @@
> >
> > static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
> >
> > +static uint8_t nand_read_byte(struct nand_chip *chip)
> > +{
> > +#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
> > + return readb(chip->IO_ADDR_R);
> > +#else
> > + return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
> > +#endif
I missed that this is a new function, not just adding 16-bit support. This
should only be used as the default; if the driver provides its own read_byte
that should be used instead.
> Are the endian assumptions in the above appropriate for all hardware?
Hmm, it looks like the non-SPL NAND code already does it like this. I guess
NAND endianness differing from native endianness just requires a custom
read_byte function.
-Scott
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