From: Ley Foon Tan <ley.foon....@intel.com>
Add NAND daughter card support, it has the following peripherals::
- NAND
- GMAC2
- I2C2
- UART0
Note, no SDMMC on NAND daughter card.
Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon....@intel.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_agilex.dtsi | 3 +
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 +
arch/arm/dts/socfpga_agilex_socdk_nand.dts | 88 +++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 arch/arm/dts/socfpga_agilex_socdk_nand.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ceaa39e4b4..34a2f4645b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -419,6 +419,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
+ socfpga_agilex_socdk_nand.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_3.dtb \
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
index c3ead2d72b..bd7f0c4182 100644
--- a/arch/arm/dts/socfpga_agilex.dtsi
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -308,6 +308,9 @@
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
+ clocks = <&clkmgr AGILEX_NAND_CLK>,
+ <&clkmgr AGILEX_NAND_X_CLK>;
+ clock-names = "nand", "nand_x";
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index 2400fad18a..56eb38d02c 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -40,6 +40,10 @@
status = "okay";
};
+&nand {
+ u-boot,dm-pre-reloc;
+};
+
&mmc {
drvsel = <3>;
smplsel = <0>;
diff --git a/arch/arm/dts/socfpga_agilex_socdk_nand.dts
b/arch/arm/dts/socfpga_agilex_socdk_nand.dts
new file mode 100644
index 0000000000..556a7b407d
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex_socdk_nand.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include "socfpga_agilex_socdk.dts"
+#include "socfpga_agilex_socdk-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,boot0 = <&nand>;
+ };
+};
+
+&gmac0 {
+ status = "disabled";
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <3800>;
+
+ mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy2: ethernet-phy@2 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "disabled";
+};
+
+&nand {
+ status = "okay";
+ nand-bus-width = <16>;
+
+ flash@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x200000 0x40000>;
+ };
+ partition@240000 {
+ label = "dtb";
+ reg = <0x240000 0x40000>;
+ };
+ partition@280000 {
+ label = "kernel";
+ reg = <0x280000 0x2000000>;
+ };
+ partition@2280000 {
+ label = "misc";
+ reg = <0x2280000 0x2000000>;
+ };
+ partition@4280000 {
+ label = "rootfs";
+ reg = <0x4280000 0x3bd0000>;
+ };
+ };
+ };
+};
\ No newline at end of file
--
2.26.2
