From: Marcel Ziswiler <marcel.ziswi...@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswi...@toradex.com>
---
arch/arm/dts/imx8mq-evk.dts | 43 +++++++++++++++++
arch/arm/dts/imx8mq-u-boot.dtsi | 10 ++--
arch/arm/dts/imx8mq.dtsi | 15 +++---
include/dt-bindings/reset/imx8mq-reset.h | 61 +++++++++++++-----------
4 files changed, 88 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 99fed35168e..82387b9cb80 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -71,12 +71,36 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@@ -386,6 +410,16 @@
status = "okay";
};
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -548,6 +582,15 @@
>;
};
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e8b5f83706e..e6448ab8ad3 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -10,23 +10,23 @@
};
-&{/soc@0} {
+&soc {
u-boot,dm-spl;
};
-&{/soc@0/bus@30000000} {
+&aips1 {
u-boot,dm-spl;
};
-&{/soc@0/bus@30400000} {
+&aips2 {
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000} {
+&aips3 {
u-boot,dm-spl;
};
-&{/soc@0/bus@32c00000} {
+&aips4 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 49eadb081b1..e9f0cdd10ab 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -94,7 +94,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <133000000>;
+ clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -320,7 +320,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -329,7 +329,7 @@
nvmem-cells = <&imx8mq_uid>;
nvmem-cell-names = "soc_unique_id";
- bus@30000000 { /* AIPS1 */
+ aips1: bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
@@ -507,7 +507,7 @@
<0x00030005 0x00000053>,
<0x00030006 0x0000005f>,
<0x00030007 0x00000071>;
- #thermal-sensor-cells = <1>;
+ #thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
@@ -784,7 +784,7 @@
};
};
- bus@30400000 { /* AIPS2 */
+ aips2: bus@30400000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
@@ -844,7 +844,7 @@
};
};
- bus@30800000 { /* AIPS3 */
+ aips3: bus@30800000 { /* AIPS3 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
@@ -1018,6 +1018,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105
IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
sec_jr1: jr@2000 {
@@ -1369,7 +1370,7 @@
};
};
- bus@32c00000 { /* AIPS4 */
+ aips4: bus@32c00000 { /* AIPS4 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
diff --git a/include/dt-bindings/reset/imx8mq-reset.h
b/include/dt-bindings/reset/imx8mq-reset.h
index 9a301082d36..705870693ec 100755
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -28,37 +28,40 @@
#define IMX8MQ_RESET_A53_L2RESET 17
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
-#define IMX8MQ_RESET_OTG2_PHY_RESET 20
-#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
-#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
-#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
-#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
-#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
-#define IMX8MQ_RESET_PCIEPHY 26
-#define IMX8MQ_RESET_PCIEPHY_PERST 27
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
-#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does
NOT support */
+#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /*
i.MX8MM/i.MX8MN does NOT support */
#define IMX8MQ_RESET_DISP_RESET 31
#define IMX8MQ_RESET_GPU_RESET 32
-#define IMX8MQ_RESET_VPU_RESET 33
-#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does
NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_DDRC1_PRST 44
-#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
-#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
-#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does
NOT support */
-#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT
support */
-#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT
support */
+#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /*
i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT
support */
+#define IMX8MQ_RESET_DDRC2_PRST 47 /*
i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does
NOT support */
+#define IMX8MQ_RESET_SW_M4C_RST 50
+#define IMX8MQ_RESET_SW_M4P_RST 51
+#define IMX8MQ_RESET_M4_ENABLE 52
-#define IMX8MQ_RESET_NUM 50
+#define IMX8MQ_RESET_NUM 53
#endif
--
2.35.1
