Re: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek MT7986 SoC

[Simon Glass]

Hi Weijie,

On Wed, 3 Aug 2022 at 21:40, Weijie Gao <weijie....@mediatek.com> wrote:
>
> This patch adds clock driver support for MediaTek MT7986 SoC
>
> Signed-off-by: Weijie Gao <weijie....@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt7986.c      | 671 +++++++++++++++++++++++++
>  include/dt-bindings/clock/mt7986-clk.h | 249 +++++++++
>  3 files changed, 921 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt7986.c
>  create mode 100644 include/dt-bindings/clock/mt7986-clk.h
>

Reviewed-by: Simon Glass <s...@chromium.org>

[..]

> new file mode 100644
> index 0000000000..11c489cd50
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt7986.c
> @@ -0,0 +1,671 @@


[..]

> +static int mt7986_topckgen_probe(struct udevice *dev)
> +{
> +       struct mtk_clk_priv *priv = dev_get_priv(dev);
> +
> +       priv->base = dev_read_addr_ptr(dev);
> +       writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);

blank line here

> +       return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
> +}
> +
> +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
> +       .name = "mt7986-clock-fixed-pll",
> +       .id = UCLASS_CLK,
> +       .of_match = mt7986_fixed_pll_compat,
> +       .probe = mt7986_fixed_pll_probe,
> +       .priv_auto = sizeof(struct mtk_clk_priv),
> +       .ops = &mtk_clk_topckgen_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_topckgen) = {
> +       .name = "mt7986-clock-topckgen",
> +       .id = UCLASS_CLK,
> +       .of_match = mt7986_topckgen_compat,
> +       .probe = mt7986_topckgen_probe,
> +       .priv_auto = sizeof(struct mtk_clk_priv),
> +       .ops = &mtk_clk_topckgen_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +static const struct udevice_id mt7986_infracfg_compat[] = {
> +       { .compatible = "mediatek,mt7986-infracfg" },
> +       {}
> +};
> +
> +static const struct udevice_id mt7986_infracfg_ao_compat[] = {
> +       { .compatible = "mediatek,mt7986-infracfg_ao" },
> +       {}
> +};
> +
> +static int mt7986_infracfg_probe(struct udevice *dev)
> +{
> +       return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
> +}
> +
> +static int mt7986_infracfg_ao_probe(struct udevice *dev)
> +{
> +       return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
> +                                       infracfg_ao_gates);
> +}
> +
> +U_BOOT_DRIVER(mtk_clk_infracfg) = {
> +       .name = "mt7986-clock-infracfg",
> +       .id = UCLASS_CLK,
> +       .of_match = mt7986_infracfg_compat,
> +       .probe = mt7986_infracfg_probe,
> +       .priv_auto = sizeof(struct mtk_clk_priv),
> +       .ops = &mtk_clk_infrasys_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
> +       .name = "mt7986-clock-infracfg-ao",
> +       .id = UCLASS_CLK,
> +       .of_match = mt7986_infracfg_ao_compat,
> +       .probe = mt7986_infracfg_ao_probe,
> +       .priv_auto = sizeof(struct mtk_cg_priv),
> +       .ops = &mtk_clk_gate_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +/* ethsys */
> +static const struct mtk_gate_regs eth_cg_regs = {
> +       .sta_ofs = 0x30,
> +};
> +
> +#define GATE_ETH(_id, _name, _parent, _shift)
>     \
> +       {                                                                     
>  \
> +               .id = _id, .parent = _parent, .regs = &eth_cg_regs,           
>  \
> +               .shift = _shift,                                              
>  \
> +               .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,        
>  \
> +       }
> +
> +static const struct mtk_gate eth_cgs[] = {
> +       GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
> +       GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
> +       GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
> +       GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 
> 14),
> +       GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 
> 15),
> +};
> +
> +static int mt7986_ethsys_probe(struct udevice *dev)
> +{
> +       return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree,
> +                                       eth_cgs);
> +}
> +
> +static int mt7986_ethsys_bind(struct udevice *dev)
> +{
> +       int ret = 0;
> +
> +#if CONFIG_IS_ENABLED(RESET_MEDIATEK)

if (CONFIG_IS_ENABLED()...

> +       ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
> +       if (ret)
> +               debug("Warning: failed to bind reset controller\n");
> +#endif
> +
> +       return ret;
> +}
> +
> +static const struct udevice_id mt7986_ethsys_compat[] = {
> +       { .compatible = "mediatek,mt7986-ethsys" },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_ethsys) = {
> +       .name = "mt7986-clock-ethsys",
> +       .id = UCLASS_CLK,
> +       .of_match = mt7986_ethsys_compat,
> +       .probe = mt7986_ethsys_probe,
> +       .bind = mt7986_ethsys_bind,
> +       .priv_auto = sizeof(struct mtk_cg_priv),
> +       .ops = &mtk_clk_gate_ops,
> +};

Regards,
Simon