On 27.07.22 15:00, Marek Behún wrote:
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the comment in SPI
node.
Signed-off-by: Marek Behún <ka...@kernel.org>
Applied to u-boot-marvell/master
Thanks,
Stefan
---
The same patch is being sent to linux,
https://lore.kernel.org/linux-arm-kernel/20220727125610.20782-1-ka...@kernel.org/
---
arch/arm/dts/armada-385-turris-omnia.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/armada-385-turris-omnia.dts
b/arch/arm/dts/armada-385-turris-omnia.dts
index 7f1478edfd..617522be17 100644
--- a/arch/arm/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/dts/armada-385-turris-omnia.dts
@@ -345,7 +345,7 @@
marvell,function = "spi0";
};
- spi0cs1_pins: spi0cs1-pins {
+ spi0cs2_pins: spi0cs2-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
@@ -380,7 +380,7 @@
};
};
- /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
+ /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
};
&uart0 {
Viele Grüße,
Stefan Roese
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Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
