Hi, After a powerup the SPL output is not seen.
[Powerup] Core: 140 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@30890000 Out: serial@30890000 Err: serial@30890000 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Only after a softreset the output from SPL can be seen. u-boot=> reset resetting ... U-Boot SPL 2022.07-rc4-00012-g4b48844ba4 (Jun 13 2022 - 21:06:16 +0200) Normal Boot Failed to find clock node. Check device tree Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 NOTICE: BL31: Built : 14:03:53, May 10 2022 U-Boot 2022.07-rc4-00012-g4b48844ba4 (Jun 13 2022 - 21:06:16 +0200) CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz Reset cause: WDOG Model: NXP i.MX8MNano DDR3L EVK board DRAM: 1 GiB Core: 140 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@30890000 Out: serial@30890000 Err: serial@30890000 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Can anyone confirm the behavior? -- Heiko
