On Tue, May 10, 2022 at 12:56 AM Peng Fan <peng....@nxp.com> wrote:
>
> > Subject: [PATCH] armv8: Fix TCR 64-bit writes
> >
> > The AArch64 TCR_ELx register is a 64-bit register, and many newer
> > architecture
> > features use bits in the upper half. So far U-Boot was igorant of those
> > bits,
> > trying to leave them alone.
> > However, in an effort to set bit 31 to 1, it failed doing so, because the
> > compiler
> > sign-extended "1 << 31", so that all bits[63:31] got set.
> >
> > Older ARMv8.0 cores don't define anything dangerous up there, but newer
> > architecture revisions do, and setting all those bits will end badly:
> > =================
> > $ qemu-system-aarch64 -cpu max ....
> > U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)
> >
> > DRAM: 1.5 GiB
> > ================= (hangs here)
> >
> > Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all upper
> > bits stay at a safe 0 value. This means no more surprises when U-Boot runs
> > on a
> > more capable CPU core.
> >
> > Reported-by: Balaji Anandapadmanaban <balaji.anandapadmana...@arm.com>
> > Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
>
> Reviewed-by: Peng Fan <peng....@nxp.com>
I ran into the same problem as you and developed the same fix. I was
about to send it out before I found your patch on the list.
Tested-by: Peter Collingbourne <p...@google.com>
Reviewed-by: Peter Collingbourne <p...@google.com>
You may also want to add:
Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR")
Peter
