Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0].
This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Signed-off-by: Rui Miguel Silva <rui.si...@linaro.org> --- arch/arm/Kconfig | 8 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/corstone1000-fvp.dts | 51 +++++++ arch/arm/dts/corstone1000-mps3.dts | 32 +++++ arch/arm/dts/corstone1000.dtsi | 164 +++++++++++++++++++++++ board/armltd/corstone1000/Kconfig | 12 ++ board/armltd/corstone1000/MAINTAINERS | 7 + board/armltd/corstone1000/Makefile | 7 + board/armltd/corstone1000/corstone1000.c | 91 +++++++++++++ configs/corstone1000_defconfig | 48 +++++++ include/configs/corstone1000.h | 52 +++++++ 11 files changed, 474 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/corstone1000-fvp.dts create mode 100644 arch/arm/dts/corstone1000-mps3.dts create mode 100644 arch/arm/dts/corstone1000.dtsi create mode 100644 board/armltd/corstone1000/Kconfig create mode 100644 board/armltd/corstone1000/MAINTAINERS create mode 100644 board/armltd/corstone1000/Makefile create mode 100644 board/armltd/corstone1000/corstone1000.c create mode 100644 configs/corstone1000_defconfig create mode 100644 include/configs/corstone1000.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0afec5155b1b..68ed0cd4709d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1341,6 +1341,12 @@ config ARCH_VEXPRESS64 select ENV_IS_IN_FLASH if MTD imply DISTRO_DEFAULTS +config TARGET_CORSTONE1000 + bool "Support Corstone1000 Platform" + select ARM64 + select PL01X_SERIAL + select DM + config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" select ARM64 @@ -2288,7 +2294,7 @@ source "arch/arm/mach-nexell/Kconfig" source "arch/arm/mach-npcm/Kconfig" source "board/armltd/total_compute/Kconfig" - +source "board/armltd/corstone1000/Kconfig" source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" source "board/Marvell/octeontx/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f67b..964403ed0a70 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1239,6 +1239,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb +dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ + corstone1000-fvp.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts new file mode 100644 index 000000000000..26b0f1b3cea6 --- /dev/null +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts new file mode 100644 index 000000000000..e3146747c2d9 --- /dev/null +++ b/arch/arm/dts/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi new file mode 100644 index 000000000000..4e46826f883a --- /dev/null +++ b/arch/arm/dts/corstone1000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig new file mode 100644 index 000000000000..709674d4cf7d --- /dev/null +++ b/board/armltd/corstone1000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CORSTONE1000 + +config SYS_BOARD + default "corstone1000" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "corstone1000" + +endif diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS new file mode 100644 index 000000000000..8c905686de76 --- /dev/null +++ b/board/armltd/corstone1000/MAINTAINERS @@ -0,0 +1,7 @@ +CORSTONE1000 BOARD +M: Rui Miguel Silva <rui.si...@linaro.org> +M: Vishnu Banavath <vishnu.banav...@arm.com> +S: Maintained +F: board/armltd/corstone1000/ +F: include/configs/corstone1000.h +F: configs/corstone1000_defconfig diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile new file mode 100644 index 000000000000..77a82c28929b --- /dev/null +++ b/board/armltd/corstone1000/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Arm Limited +# (C) Copyright 2022 Linaro +# Rui Miguel Silva <rui.si...@linaro.org> + +obj-y := corstone1000.o diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c new file mode 100644 index 000000000000..4f4b96a095c2 --- /dev/null +++ b/board/armltd/corstone1000/corstone1000.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva <rui.si...@linaro.org> + */ + +#include <common.h> +#include <dm.h> +#include <netdev.h> +#include <dm/platform_data/serial_pl01x.h> +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> + +static struct mm_region corstone1000_mem_map[] = { + { + /* CVM */ + .virt = 0x02000000UL, + .phys = 0x02000000UL, + .size = 0x02000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* QSPI */ + .virt = 0x08000000UL, + .phys = 0x08000000UL, + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Host Peripherals */ + .virt = 0x1A000000UL, + .phys = 0x1A000000UL, + .size = 0x26000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* USB */ + .virt = 0x40200000UL, + .phys = 0x40200000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* ethernet */ + .virt = 0x40100000UL, + .phys = 0x40100000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCVM */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = corstone1000_mem_map; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig new file mode 100644 index 000000000000..4f6082770f89 --- /dev/null +++ b/configs/corstone1000_defconfig @@ -0,0 +1,48 @@ +CONFIG_ARM=y +CONFIG_TARGET_CORSTONE1000=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" +CONFIG_IDENT_STRING=" corstone1000 aarch64 " +CONFIG_SYS_LOAD_ADDR=0x82100000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" +CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" +CONFIG_CONSOLE_RECORD=y +CONFIG_LOGLEVEL=7 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="corstone1000# " +# CONFIG_CMD_CONSOLE is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_LOADM=y +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_OF_CONTROL=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_SMC911X=y +CONFIG_PHY=y +CONFIG_RAM=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h new file mode 100644 index 000000000000..6bc0fc976018 --- /dev/null +++ b/include/configs/corstone1000.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva <rui.si...@linaro.org> + * Abdellatif El Khlifi <abdellatif.elkhl...@arm.com> + * + * Configuration for Corstone1000. Parts were derived from other ARM + * configurations. + */ + +#ifndef __CORSTONE1000_H +#define __CORSTONE1000_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_HZ 1000 + +#define V2M_BASE 0x80000000 + +#define CONFIG_PL011_CLOCK 50000000 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define CONFIG_ENV_SECT_SIZE SZ_64K + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usb_pgood_delay=250\0" \ + "boot_bank_flag=0x08002000\0" \ + "kernel_addr_bank_0=0x083EE000\0" \ + "kernel_addr_bank_1=0x0936E000\0" \ + "retrieve_kernel_load_addr=" \ + "if itest.l *${boot_bank_flag} == 0; then " \ + "setenv kernel_addr $kernel_addr_bank_0;" \ + "else " \ + "setenv kernel_addr $kernel_addr_bank_1;" \ + "fi;" \ + "\0" \ + "kernel_addr_r=0x88200000\0" + +#endif -- 2.36.1
