Dear =?ISO-8859-1?Q?Matthias_Wei=DFer?=, In message <[email protected]> you wrote: > > > You said you had enabled the data cache, so why do you think these > > accesses are not cached? > > Please see arch/arm/lib/cache-cp15.c > The code there creates 4096 page table entries (1MB each) for the whole > 4GB address space and initializes each entry in a way that it is not > cacheable (mmu_setup():71). It then changes the page table entries which > are pointing to a RAM area to make these, and only these, cacheable > (dram_bank_mmu_setup():57).
You did not mention this before. You just said: "I enabled dcache" which for e sounds as if you did this globally. Well, I'm not an export for AT91 in any way... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] The human mind treats a new idea the way the body treats a strange protein - it rejects it. - P. Medawar _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
