MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.

Without this delays in R5 SPL are 10x off.

Signed-off-by: Vignesh Raghavendra <vigne...@ti.com>
---
 arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 749bc717f3..a17e61eccf 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -40,7 +40,7 @@
                compatible = "ti,omap5430-timer";
                reg = <0x0 0x40400000 0x0 0x80>;
                ti,timer-alwon;
-               clock-frequency = <25000000>;
+               clock-frequency = <250000000>;
                u-boot,dm-spl;
        };
 
-- 
2.35.1

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