Re: [PATCH u-boot-mvebu 2/3] arm: mvebu: a37xx: Map CCI-400 and AP BootROM address space

[Stefan Roese]

On 2/15/22 00:28, Pali Rohár wrote:

In function build_mem_map() prepares also mapping for CCI-400 and
AP BootROM address space.

A53 AP BootROM by default starts at address 0xfff00000 and is 16 kB long.
CCI-400 in new TF-A version starts at address 0xfe000000 and is 64 kB long.

Physical addresses are read directly from mvebu registers, so if TF-A
remaps it in future then it would not cause any issue.

Signed-off-by: Pali Rohár <p...@kernel.org>

Reviewed-by: Stefan Roese <s...@denx.de>

Thanks,
Stefan

---
  arch/arm/mach-mvebu/armada3700/cpu.c | 22 +++++++++++++++++++++-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c 
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 9da0d08f947c..e01fea130022 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -40,8 +40,10 @@
  #define MVEBU_CPU_DEC_WIN_REMAP(w)    (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
  #define MVEBU_CPU_DEC_WIN_GRANULARITY 16
  #define MVEBU_CPU_DEC_WINS            5
+#define MVEBU_CPU_DEC_CCI_BASE         (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
+#define MVEBU_CPU_DEC_ROM_BASE         (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)

-#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)

+#define MAX_MEM_MAP_REGIONS            (MVEBU_CPU_DEC_WINS + 4)

#define A3700_PTE_BLOCK_NORMAL \

        (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
@@ -104,8 +106,26 @@ static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, 
u32 *size)
  static void build_mem_map(void)
  {
        int win, region;
+       u32 reg;

region = 1;

+
+       /* CCI-400 */
+       reg = readl(MVEBU_CPU_DEC_CCI_BASE);
+       mvebu_mem_map[region].phys = reg << 20;
+       mvebu_mem_map[region].virt = reg << 20;
+       mvebu_mem_map[region].size = 0x10000;
+       mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
+       ++region;
+
+       /* AP BootROM */
+       reg = readl(MVEBU_CPU_DEC_ROM_BASE);
+       mvebu_mem_map[region].phys = reg << 20;
+       mvebu_mem_map[region].virt = reg << 20;
+       mvebu_mem_map[region].size = 0x4000;
+       mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
+       ++region;
+
        for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
                u32 base, tgt, size;
                u64 attrs;

Viele Grüße,
Stefan Roese

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