Enable a periodic timer on NPCM SoCs and implement
the get_count timer ops.
Signed-off-by: Stanley Chu <ys...@nuvoton.com>
---
v3:
- use driver data for clock setting on different chips
- remove unnecessary code of zeroing priv variables
- more help description in Kconfig
v2:
- calculate the prescale value, not hardcode
---
drivers/timer/Kconfig | 9 +++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 115 +++++++++++++++++++++++++++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..abcc736492 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,15 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+ NPCM timer module has 5 down-counting timers, only the first timer
+ is used to implement timer ops. No support for early timer and
+ boot timer.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 0000000000..4562a6f231
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10 /* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE
- 1)
+
+enum input_clock_type {
+ INPUT_CLOCK_FIXED, /* input clock rate is fixed */
+ INPUT_CLOCK_NON_FIXED
+};
+
+/**
+ * struct npcm_timer_priv - private data for npcm timer driver
+ * npcm timer is a 24-bits down-counting timer.
+ *
+ * @last_count: last hw counter value
+ * @counter: the value to be returned for get_count ops
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is counting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ enum input_clock_type type = dev_get_driver_data(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (type == INPUT_CLOCK_NON_FIXED) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+ * Configure timer and start
+ * periodic mode
+ * timer clock rate = input clock / prescale
+ */
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer", .data = INPUT_CLOCK_FIXED},
+ { .compatible = "nuvoton,npcm750-timer", .data = INPUT_CLOCK_NON_FIXED},
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto = sizeof(struct npcm_timer_priv),
+ .probe = npcm_timer_probe,
+ .ops = &npcm_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
