> -----Original Message----- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: 2022年1月29日 1:37 > To: Jaehoon Chung <jh80.ch...@samsung.com>; u-boot@lists.denx.de > Cc: sba...@denx.de; Bough Chen <haibo.c...@nxp.com>; Igor Opaniuk > <igor.opan...@foundries.io>; Peng Fan <peng....@nxp.com> > Subject: Re: [PATCH] Revert "mmc: fsl_esdhc_imx: add wait_dat0() support" > > On 1/28/22 08:30, Jaehoon Chung wrote: > > Hi Marek, > > Hi, > > > On 1/28/22 12:40, Marek Vasut wrote: > >> This reverts commit b5874b552ffa09bc1dc5dec6b5dd376c62dab45d. > >> > >> It seems the iMX8MM SDHC controller always reports DAT0 line status > >> as zero after voltage switch at the end of mmc_switch_voltage(), even > >> if it is supposed to be high and scope confirms the DAT0 is high. > >> Reverting this patch makes SDR104 work on iMX8MM, however, it is not > >> clear why the DAT0 status is not correctly reported by the > >> controller. > > > > I didn't have an imx8mm board, so I wonder that other boards which is using > fsl_esdhci_imx driver have same problem. > > I have multiple 8mm, just not the 8mm-evk. > > > I'm not sure...I remember that some controller doesn't support a busy > > signal. > > In kernel driver, also doesn't report correct status? > > Kernel doesn't use this DAT0 readback, that's why it works in kernel. > > U-Boot has been augmented with this DAT0 readback some time ago, I just > noticed it on an 8mm board recently that it doesn't really work. There is > also no > errata. > > I think it would be good to have NXP check this.
Hi,
The issue you meet should be related to one patch that was revert recently,
refer to
Commit f132aab40327 " Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
to control card clock output""
The issue you meet seems the same as what I mentioned in my original commit
log, I paste in the end.
Revert this patch because we did find this patch has some side effect, like
enlarge the whole boot up time about 20s.
If you will, you can add back this patch on your side, and test it.
I will send one new patch this week, to fix issue and avoid side effect.
Best Regards
Haibo Chen
commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2
Author: Haibo Chen <haibo.c...@nxp.com>
Date: Wed Mar 3 17:05:46 2021 +0800
mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the
FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Tested-by: Tim Harvey <thar...@gateworks.com>
Signed-off-by: Haibo Chen <haibo.c...@nxp.com>
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