[PATCH v1 13/15] arm: dts: rockchip: move all rk3288-veyron u-boot related properties

[Johan Jonker]

In order to sync rk3288-veyron related DT files
all u-boot properties have to move to rk3288-veyron-u-boot.dtsi

Signed-off-by: Johan Jonker <jbx6...@gmail.com>
---
 arch/arm/dts/rk3288-veyron-u-boot.dtsi | 42 ++++++++++++++++++++++++++
 arch/arm/dts/rk3288-veyron.dtsi        | 19 ------------
 2 files changed, 42 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi 
b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index 2afbf96d..c8b33fea 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -5,6 +5,12 @@
 
 #include "rk3288-u-boot.dtsi"
 
+/ {
+       chosen {
+               u-boot,spl-boot-order = &spi_flash;
+       };
+};
+
 &dmc {
        logic-supply = <&vdd_logic>;
        rockchip,odt-disable-freq = <333000000>;
@@ -25,7 +31,43 @@
        >;
 };
 
+&gpio3 {
+       u-boot,dm-pre-reloc;
+};
+
 &gpio7 {
        u-boot,dm-pre-reloc;
 };
 
+&gpio8 {
+       u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+       u-boot,dm-pre-reloc;
+};
+
+&rk808 {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+       u-boot,dm-pre-reloc;
+};
+
+&spi2 {
+       u-boot,dm-pre-reloc;
+};
+
+&spi_flash {
+       u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+       u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index cd0e7362..434b0d49 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -16,7 +16,6 @@
 
        chosen {
                stdout-path = &uart2;
-               u-boot,spl-boot-order = &spi_flash;
        };
 
        firmware {
@@ -264,10 +263,8 @@
 
 &spi2 {
        status = "okay";
-       u-boot,dm-pre-reloc;
 
        spi_flash: spiflash@0 {
-               u-boot,dm-pre-reloc;
                compatible = "spidev", "jedec,spi-nor";
                spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 
pro */
                reg = <0>;
@@ -280,7 +277,6 @@
        clock-frequency = <400000>;
        i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
        i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
-       u-boot,dm-pre-reloc;
 
        rk808: pmic@1b {
                compatible = "rockchip,rk808";
@@ -293,7 +289,6 @@
                rockchip,system-power-controller;
                wakeup-source;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
 
                vcc1-supply = <&vcc33_sys>;
                vcc2-supply = <&vcc33_sys>;
@@ -535,7 +530,6 @@
 
 &uart2 {
        status = "okay";
-       u-boot,dm-pre-reloc;
        reg-shift = <2>;
 };
 
@@ -575,7 +569,6 @@
 };
 
 &pinctrl {
-       u-boot,dm-pre-reloc;
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <
                /* Common for sleep and wake, but no owners */
@@ -800,15 +793,3 @@
        assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
        assigned-clock-parents = <&cru SCLK_OTGPHY0>;
 };
-
-&sdmmc {
-       u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
-       u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
-       u-boot,dm-pre-reloc;
-};
-- 
2.20.1