[PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII

[Aswath Govindraju]

Add support for QSGMII multilink configuration.

Signed-off-by: Aswath Govindraju <a-govindr...@ti.com>
---
 .../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi |  5 +++++
 arch/arm/dts/k3-j721e-common-proc-board.dts        | 14 +++++++++++---
 arch/arm/dts/k3-j721e-r5-common-proc-board.dts     | 12 ++++++++++--
 3 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 938e978a6b66..677a72d2a241 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -242,3 +242,8 @@
        assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
        assigned-clock-parents = <&wiz0_pll1_refclk>;
 };
+
+&serdes0_qsgmii_link {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts 
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 8bd02d9e28ad..f3b6302a4317 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -345,7 +345,7 @@
 };
 
 &serdes_ln_ctrl {
-       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, 
<J721E_SERDES0_LANE1_PCIE0_LANE1>,
+       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, 
<J721E_SERDES0_LANE1_QSGMII_LANE2>,
                      <J721E_SERDES1_LANE0_PCIE1_LANE0>, 
<J721E_SERDES1_LANE1_PCIE1_LANE1>,
                      <J721E_SERDES2_LANE0_PCIE2_LANE0>, 
<J721E_SERDES2_LANE1_PCIE2_LANE1>,
                      <J721E_SERDES3_LANE0_USB3_0_SWAP>, 
<J721E_SERDES3_LANE1_USB3_0>,
@@ -671,8 +671,8 @@
 };
 
 &serdes0 {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>;
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 
CDNS_SIERRA_PLL_CMNLC1>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
 
        serdes0_pcie_link: phy@0 {
                reg = <0>;
@@ -681,6 +681,14 @@
                cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz0 1>;
        };
+
+       serdes0_qsgmii_link: phy@1 {
+               reg = <1>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_QSGMII>;
+               resets = <&serdes_wiz0 2>;
+       };
 };
 
 &serdes1 {
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts 
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 8299463c3e01..5362c528703d 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -374,8 +374,8 @@
 };
 
 &serdes0 {
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>;
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 
CDNS_SIERRA_PLL_CMNLC1>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
 
        serdes0_pcie_link: link@0 {
                reg = <0>;
@@ -384,4 +384,12 @@
                cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz0 1>;
        };
+
+       serdes0_qsgmii_link: phy@1 {
+               reg = <1>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_QSGMII>;
+               resets = <&serdes_wiz0 2>;
+       };
 };
-- 
2.17.1