pá 14. 1. 2022 v 12:44 odesílatel Michal Simek <michal.si...@xilinx.com> napsal:
>
> From: Shravya Kumbham <shravya.kumb...@xilinx.com>
>
> Update dma name and add #dma-cells properties to fix dtbs_check
> warnings.
>
> Signed-off-by: Shravya Kumbham <shravya.kumb...@xilinx.com>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
> ---
>
> arch/arm/dts/zynqmp.dtsi | 48 ++++++++++++++++++++++++++--------------
> 1 file changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
> index 1331cec36f34..755a4ed2e515 100644
> --- a/arch/arm/dts/zynqmp.dtsi
> +++ b/arch/arm/dts/zynqmp.dtsi
> @@ -265,7 +265,7 @@
> };
>
> /* GDMA */
> - fpd_dma_chan1: dma@fd500000 {
> + fpd_dma_chan1: dma-controller@fd500000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd500000 0x0 0x1000>;
> @@ -276,9 +276,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14e8>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan2: dma@fd510000 {
> + fpd_dma_chan2: dma-controller@fd510000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd510000 0x0 0x1000>;
> @@ -289,9 +290,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14e9>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan3: dma@fd520000 {
> + fpd_dma_chan3: dma-controller@fd520000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd520000 0x0 0x1000>;
> @@ -302,9 +304,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14ea>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan4: dma@fd530000 {
> + fpd_dma_chan4: dma-controller@fd530000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd530000 0x0 0x1000>;
> @@ -315,9 +318,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14eb>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan5: dma@fd540000 {
> + fpd_dma_chan5: dma-controller@fd540000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd540000 0x0 0x1000>;
> @@ -328,9 +332,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14ec>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan6: dma@fd550000 {
> + fpd_dma_chan6: dma-controller@fd550000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd550000 0x0 0x1000>;
> @@ -341,9 +346,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14ed>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan7: dma@fd560000 {
> + fpd_dma_chan7: dma-controller@fd560000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd560000 0x0 0x1000>;
> @@ -354,9 +360,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14ee>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> - fpd_dma_chan8: dma@fd570000 {
> + fpd_dma_chan8: dma-controller@fd570000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd570000 0x0 0x1000>;
> @@ -367,6 +374,7 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x14ef>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> + #dma-cells = <1>;
> };
>
> gic: interrupt-controller@f9010000 {
> @@ -396,7 +404,7 @@
> * These dma channels, Users should ensure that these dma
> * Channels are allowed for non secure access.
> */
> - lpd_dma_chan1: dma@ffa80000 {
> + lpd_dma_chan1: dma-controller@ffa80000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa80000 0x0 0x1000>;
> @@ -407,9 +415,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x868>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan2: dma@ffa90000 {
> + lpd_dma_chan2: dma-controller@ffa90000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa90000 0x0 0x1000>;
> @@ -420,9 +429,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x869>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan3: dma@ffaa0000 {
> + lpd_dma_chan3: dma-controller@ffaa0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaa0000 0x0 0x1000>;
> @@ -433,9 +443,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86a>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan4: dma@ffab0000 {
> + lpd_dma_chan4: dma-controller@ffab0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffab0000 0x0 0x1000>;
> @@ -446,9 +457,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86b>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan5: dma@ffac0000 {
> + lpd_dma_chan5: dma-controller@ffac0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffac0000 0x0 0x1000>;
> @@ -459,9 +471,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86c>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan6: dma@ffad0000 {
> + lpd_dma_chan6: dma-controller@ffad0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffad0000 0x0 0x1000>;
> @@ -472,9 +485,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86d>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan7: dma@ffae0000 {
> + lpd_dma_chan7: dma-controller@ffae0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffae0000 0x0 0x1000>;
> @@ -485,9 +499,10 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86e>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> - lpd_dma_chan8: dma@ffaf0000 {
> + lpd_dma_chan8: dma-controller@ffaf0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaf0000 0x0 0x1000>;
> @@ -498,6 +513,7 @@
> #stream-id-cells = <1>;
> iommus = <&smmu 0x86f>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> + #dma-cells = <1>;
> };
>
> mc: memory-controller@fd070000 {
> --
> 2.34.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
