Hi Tudor > > On 11/18/21 12:13 PM, JaimeLiao wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > Adding Macronix Octal flash for Octal DTR support. > > > > The octaflash series can be divided into the following types: > > > > MX25 series : Serial NOR Flash. > > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb) > > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation. > > LW/UW series : Support simultaneous Read-while-Write operation in multiple > > bank architecture. Read-while-write feature which means read > > data one bank while another bank is programing or erasing. > > > > MX25LM : 3.0V Octal I/O > > > > -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf > > > > MX25UM : 1.8V Octal I/O > > > > -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf > > > > MX66LM : 3.0V Octal I/O with stacked die > > > > -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf > > > > MX66UM : 1.8V Octal I/O with stacked die > > > > -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf > > > > MX25LW : 3.0V Octal I/O with Read-while-Write > > MX25UW : 1.8V Octal I/O with Read-while-Write > > MX66LW : 3.0V Octal I/O with Read-while-Write and stack die > > MX66UW : 1.8V Octal I/O with Read-while-Write and stack die > > > > About LW/UW series, please contact us freely if you have any > > questions. For adding Octal NOR Flash IDs, we have validated > > each Flash on plateform zynq-picozed. > > > > Signed-off-by: JaimeLiao <jaimeliao...@gmail.com> > > --- > > drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > > index cb3a08872d..5c13ea3a78 100644 > > --- a/drivers/mtd/spi/spi-nor-ids.c > > +++ b/drivers/mtd/spi/spi-nor-ids.c > > @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = { > > { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, > > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, > > { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, > > - { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66lm1g45g", 0xc2853b, 0, 32 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > which one of all these flashes (including the ones from below) support > SFDP and which not? Which can discover the octal dtr method by parsing > SFDP and which not? Depending on these those flash_info flags may change.
I agree that we need a method for octal dtr support on flash which didn't include SFDP but the patch of method is separate with Octal DTR patch. > Why do you need SPI_NOR_4B_OPCODES, can't this support be discovered > when parsing SFDP? How about SECT_4K? > > I know for sure there are variants of mx66lm1g45g that do not support > SFDP, and flavors that do support SFDP. How you'll differentiate between > the two flavors of the same flash? > > I chose to SKIP SFDP parsing for mx66lm1g45g as there's no infrastructure > to handle its case, neither in linux, nor u-boot. > Here's what I proposed for now: > https://lore.kernel.org/all/20211103234950.202289-3-tudor.amba...@microchip.com/ > > > Cheers, > ta > > > + { INFO("mx25lm51245g", 0xc2853a, 0, 16 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25lw51245g", 0xc2863a, 0, 16 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25lm25645g", 0xc28539, 0, 8 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66um1g45g", 0xc2803b, 0, 32 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx66uw1g45g", 0xc2813b, 0, 32 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25um51245g", 0xc2803a, 0, 16 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw51245g", 0xc2813a, 0, 16 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw51345g", 0xc2843a, 0, 16 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25um25645g", 0xc28039, 0, 8 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw25645g", 0xc28139, 0, 8 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25um25345g", 0xc28339, 0, 8 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw25345g", 0xc28439, 0, 8 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw12845g", 0xc28138, 0, 4 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw12a45g", 0xc28938, 0, 4 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw12345g", 0xc28438, 0, 4 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw6445g", 0xc28137, 0, 2 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mx25uw6345g", 0xc28437, 0, 2 * 1024, 4096, SECT_4K | > > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, > > #endif > > > > #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ > > -- > > 2.17.1 > > >
