On P2020DS and MPC8572DS, the link to SGMII card which use Vitesse
VSC8234 PHY can't come up. Current TBI PHY settings(TBICR_SETTINGS)
for SGMII mode cause link problems.
Revert commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4, and fix it.
Signed-off-by: Zhao Chenhui <b26...@freescale.com>
---
drivers/net/tsec.c | 2 +-
include/configs/XPEDITE5370.h | 7 +++++++
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9b5dd92..862b0db 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -290,10 +290,10 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t
*phyregs,
| TBIANA_FULL_DUPLEX \
)
-/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
#ifndef CONFIG_TSEC_TBICR_SETTINGS
#define TBICR_SETTINGS ( \
TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 8225fff..aa1d1a8 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -370,6 +370,13 @@ extern unsigned long get_board_ddr_clk(unsigned long
dummy);
#define TSEC2_PHYIDX 0
#define CONFIG_HAS_ETH1
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
/*
* Command configuration.
*/
--
1.6.4.1
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