On Sat, 11 Sep 2021 14:45:31 -0500 Samuel Holland <sam...@sholland.org> wrote:
> The sunxi clock driver exposes a reset controller, so it selects the > reset controller framework. Ensure that dependency is also satisfied > when building the driver for the SPL. > > Signed-off-by: Samuel Holland <sam...@sholland.org> Reviewed-by: Andre Przywara <andre.przyw...@arm.com> Cheers, Andre > --- > > drivers/clk/sunxi/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig > index bf084fa7a84..43c321692cf 100644 > --- a/drivers/clk/sunxi/Kconfig > +++ b/drivers/clk/sunxi/Kconfig > @@ -2,6 +2,7 @@ config CLK_SUNXI > bool "Clock support for Allwinner SoCs" > depends on CLK && ARCH_SUNXI > select DM_RESET > + select SPL_DM_RESET if SPL_CLK > default y > help > This enables support for common clock driver API on Allwinner
