On Mon, 25 Oct 2021 at 08:34, Nico Cheng <nico.ch...@rock-chips.com> wrote:
>
> We configured the drive strength and security of EMMC in
> arch_cpu_init().
>
> Signed-off-by: Nico Cheng <nico.ch...@rock-chips.com>
> ---
>
> Changes in v2:
> We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to
> secure.
> Modify comments to make them more explicit.
>
> arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c
> b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 973b4f9dcb..1a62052731 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -13,6 +13,14 @@
>
> #define PMUGRF_BASE 0xfdc20000
> #define GRF_BASE 0xfdc60000
> +#define GRF_GPIO1B_DS_2 0x218
> +#define GRF_GPIO1B_DS_3 0x21c
> +#define GRF_GPIO1C_DS_0 0x220
> +#define GRF_GPIO1C_DS_1 0x224
> +#define GRF_GPIO1C_DS_2 0x228
> +#define GRF_GPIO1C_DS_3 0x22c
> +#define SGRF_BASE 0xFDD18000
> +#define SGRF_SOC_CON4 0x10
>
> /* PMU_GRF_GPIO0D_IOMUX_L */
> enum {
> @@ -81,5 +89,16 @@ void board_debug_uart_init(void)
>
> int arch_cpu_init(void)
> {
> +#ifdef CONFIG_SPL_BUILD
> + /* Set the emmc sdmmc0 to secure */
> + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (0x3 << 11 | 0x1 << 4));
Please introduce symbolic constants (or at least a C99 'const'
expressions with a suitable names) to clarify what bits[12:11]
and bit[4] control?
> + /* set the emmc driver strength to level 2 */
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
> +#endif
> return 0;
> }
> --
> 2.17.1
>
>
>
