On Thu, Oct 21, 2021 at 4:01 AM Roman Bacik <roman.ba...@broadcom.com> wrote:
>
> From: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com>
>
> IPROC qspi driver supports both BSPI and MSPI modes.
>
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com>
> Signed-off-by: Bharat Gooty <bharat.go...@broadcom.com>
> Acked-by: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com>
>
> Signed-off-by: Roman Bacik <roman.ba...@broadcom.com>
> ---
>
> Changes in v3:
> - fix warning by including linux/delay.h
> - change ofdata_to_platdata to of_to_plat
> - change priv_auto_alloc_size to priv_auto
>
> Changes in v2:
> - remove include spi-nor.h
> - define and use named BITs for writing register values
> - remove bspi_set_4byte_mode() method
>
> drivers/spi/Kconfig | 6 +
> drivers/spi/Makefile | 1 +
> drivers/spi/iproc_qspi.c | 713 +++++++++++++++++++++++++++++++++++++++
> drivers/spi/iproc_qspi.h | 20 ++
> 4 files changed, 740 insertions(+)
> create mode 100644 drivers/spi/iproc_qspi.c
> create mode 100644 drivers/spi/iproc_qspi.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index d07e9a28af82..e76fadef32dd 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -178,6 +178,12 @@ config ICH_SPI
> access the SPI NOR flash on platforms embedding this Intel
> ICH IP core.
>
> +config IPROC_QSPI
> + bool "QSPI driver for BCM iProc QSPI Controller"
> + help
> + This selects the BCM iProc QSPI controller.
> + This driver support spi flash single, quad and memory reads.
> +
> config KIRKWOOD_SPI
> bool "Marvell Kirkwood SPI Driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index d2f24bccefd3..869763187062 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
> obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
> obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
> obj-$(CONFIG_ICH_SPI) += ich.o
> +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
> obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
> new file mode 100644
> index 000000000000..08881bf61764
> --- /dev/null
> +++ b/drivers/spi/iproc_qspi.c
> @@ -0,0 +1,713 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020-2021 Broadcom
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include "iproc_qspi.h"
> +
> +/* 175MHz */
> +#define QSPI_AXI_CLK 175000000
> +#define QSPI_DEF_SCK_FREQ 50000000
> +#define QSPI_WAIT_TIMEOUT_MS 200U
> +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3))
> +
> +/* Chip attributes */
> +#define SPBR_MIN 8U
> +#define SPBR_MAX 255U
> +#define NUM_CDRAM 16U
> +
> +#define CDRAM_PCS0 2
> +#define CDRAM_CONT BIT(7)
> +#define CDRAM_BITS_EN BIT(6)
> +#define CDRAM_QUAD_MODE BIT(8)
> +#define CDRAM_RBIT_INPUT BIT(10)
> +#define MSPI_SPE BIT(6)
> +#define MSPI_CONT_AFTER_CMD BIT(7)
> +
> +/* Register fields */
> +#define MSPI_SPCR0_MSB_BITS_8 0x00000020
> +#define BSPI_RAF_CONTROL_START_MASK 0x00000001
> +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
> +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
> +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x00010000
> +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0
> +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16
> +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3
> +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1
> +#define BSPI_STRAP_OVERRIDE_SHIFT 0
> +
> +/* MSPI registers */
> +#define MSPI_SPCR0_LSB_REG 0x000
> +#define MSPI_SPCR0_MSB_REG 0x004
> +#define MSPI_SPCR1_LSB_REG 0x008
> +#define MSPI_SPCR1_MSB_REG 0x00c
> +#define MSPI_NEWQP_REG 0x010
> +#define MSPI_ENDQP_REG 0x014
> +#define MSPI_SPCR2_REG 0x018
> +#define MSPI_STATUS_REG 0x020
> +#define MSPI_CPTQP_REG 0x024
> +#define MSPI_TXRAM_REG 0x040
> +#define MSPI_RXRAM_REG 0x0c0
> +#define MSPI_CDRAM_REG 0x140
> +#define MSPI_WRITE_LOCK_REG 0x180
> +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
> +
> +/* BSPI registers */
> +#define BSPI_REVISION_ID_REG 0x000
> +#define BSPI_SCRATCH_REG 0x004
> +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
> +#define BSPI_BUSY_STATUS_REG 0x00c
> +#define BSPI_INTR_STATUS_REG 0x010
> +#define BSPI_B0_STATUS_REG 0x014
> +#define BSPI_B0_CTRL_REG 0x018
> +#define BSPI_B1_STATUS_REG 0x01c
> +#define BSPI_B1_CTRL_REG 0x020
> +#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024
> +#define BSPI_FLEX_MODE_ENABLE_REG 0x028
> +#define BSPI_BITS_PER_CYCLE_REG 0x02C
> +#define BSPI_BITS_PER_PHASE_REG 0x030
> +#define BSPI_CMD_AND_MODE_BYTE_REG 0x034
> +#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038
> +#define BSPI_XOR_VALUE_REG 0x03C
> +#define BSPI_XOR_ENABLE_REG 0x040
> +#define BSPI_PIO_MODE_ENABLE_REG 0x044
> +#define BSPI_PIO_IODIR_REG 0x048
> +#define BSPI_PIO_DATA_REG 0x04C
> +
> +/* RAF registers */
> +#define BSPI_RAF_START_ADDRESS_REG 0x00
> +#define BSPI_RAF_NUM_WORDS_REG 0x04
> +#define BSPI_RAF_CTRL_REG 0x08
> +#define BSPI_RAF_FULLNESS_REG 0x0C
> +#define BSPI_RAF_WATERMARK_REG 0x10
> +#define BSPI_RAF_STATUS_REG 0x14
> +#define BSPI_RAF_READ_DATA_REG 0x18
> +#define BSPI_RAF_WORD_CNT_REG 0x1C
> +#define BSPI_RAF_CURR_ADDR_REG 0x20
> +
> +#define XFER_DUAL BIT(30)
> +#define XFER_QUAD BIT(31)
> +
> +#define FLASH_BIT BIT(0)
> +#define MAST_N_BOOT_BIT BIT(0)
> +#define FLEX_MODE_ENABLE_BIT BIT(0)
> +#define WRITE_LOCK_BIT BIT(0)
> +
> +/* state */
> +enum bcm_qspi_state {
> + QSPI_STATE_DISABLED,
> + QSPI_STATE_MSPI,
> + QSPI_STATE_BSPI
> +};
> +
> +/**
> + * struct bcmspi_priv - qspi private structure
> + *
> + * @max_hz: device transfer speed
> + * @spi_mode: spi mode (SPI_... flags)
> + * @frequency: spi max frequency
> + * @state: device state (MSPI/BSPI)
> + * @bspi_addr: bspi read address
> + * @mspi_16bit: mspi transfer mode
> + * @use_bspi: flag to indicate BSPI use for read operation
> + * @mspi: mspi registers block address
> + * @bspi: bspi registers block address
> + * @bspi_raf: bspi raf registers block address
> + */
> +struct bcmspi_priv {
> + uint max_hz;
> + uint spi_mode;
> + s32 frequency;
> + enum bcm_qspi_state state;
> + u32 bspi_addr;
> + int mspi_16bit;
> + int mode_4byte;
> + int use_bspi;
> + void __iomem *mspi;
> + void __iomem *bspi;
> + void __iomem *bspi_raf;
> +};
> +
> +static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
> +{
> + writel(0, priv->bspi + BSPI_B0_CTRL_REG);
> + writel(0, priv->bspi + BSPI_B1_CTRL_REG);
> + writel(FLASH_BIT, priv->bspi + BSPI_B0_CTRL_REG);
> + writel(FLASH_BIT, priv->bspi + BSPI_B1_CTRL_REG);
> +}
> +
> +static int bcmspi_enable_bspi(struct bcmspi_priv *priv)
> +{
> + if (priv->state == QSPI_STATE_BSPI)
> + return 0;
> +
> + /* Disable write lock */
> + writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
> + /* Flush prefetch buffers */
> + bspi_flush_prefetch_buffers(priv);
> + /* Switch to BSPI */
> + writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
> + /* Update state */
> + priv->state = QSPI_STATE_BSPI;
> +
> + return 0;
> +}
> +
> +static int bcmspi_disable_bspi(struct bcmspi_priv *priv)
> +{
> + if (priv->state == QSPI_STATE_MSPI)
> + return 0;
> +
> + /* Switch to MSPI if not yet */
> + if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
> + ulong start = get_timer(0);
> +
> + while (get_timer(start) <
> + QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
> + if ((readl(priv->bspi + BSPI_BUSY_STATUS_REG) & 1)
> + == 0) {
> + writel(MAST_N_BOOT_BIT, priv->bspi +
> + BSPI_MAST_N_BOOT_CTRL_REG);
> + udelay(1);
> + break;
> + }
> + udelay(1);
> + }
> + if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) != 1)
> + return -1;
> + }
> +
> + /* Update state */
> + priv->state = QSPI_STATE_MSPI;
> +
> + return 0;
> +}
> +
> +static void bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
> +{
> + u32 status;
> + uint words;
> + int aligned;
> +
> + /* Flush data from the previous session (unlikely) */
> + for (;;) {
> + status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
> + if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
> + readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG);
> + continue;
> + }
> + if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK))
> + break;
> + }
> +
> + /* Transfer is in words */
> + words = (bytes + 3) / 4;
> +
> + /* Setup hardware */
> + if (priv->mode_4byte) {
> + u32 val = priv->bspi_addr & 0xFF000000;
> +
> + if (val != readl(priv->bspi +
> BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
> + writel(val,
> + priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
> + bspi_flush_prefetch_buffers(priv);
> + }
> + }
> + writel(priv->bspi_addr & 0x00FFFFFF,
> + priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG);
> + writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG);
> + writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG);
> +
> + /* Kick off */
> + writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf +
> BSPI_RAF_CTRL_REG);
> +
> + /* Reading the data */
> + aligned = DWORD_ALIGNED(rx);
> + while (bytes) {
> + status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
> + if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
> + u32 data = le32_to_cpu(readl(priv->bspi_raf +
> + BSPI_RAF_READ_DATA_REG));
> +
> + /* Check if we can use the whole word */
> + if (aligned && bytes >= 4) {
> + /*
> + * RAF is LE only,
> + * convert data to host endianness
> + */
> + *(u32 *)rx = le32_to_cpu(data);
> + rx += 4;
> + bytes -= 4;
> + } else {
> + uint chunk = min(bytes, 4U);
> +
> + /* Read out bytes one by one */
> + while (chunk) {
> + *rx++ = (u8)data;
> + data >>= 8;
> + chunk--;
> + bytes--;
> + }
> + }
> +
> + continue;
> + }
> + if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
> + /* FIFO is empty and the session is done */
> + break;
> + }
> + }
> +}
> +
> +static int bspi_read(struct bcmspi_priv *priv, const u8 *tx, u8 *rx,
> + uint bytes, ulong flags)
> +{
> + int idx = priv->mode_4byte ? 2 : 1;
> + /* Check the address */
> + if (flags & SPI_XFER_BEGIN) {
> + u32 addr;
> +
> + /* Drop if the first transfer doesn't contain full address */
> + if (bytes < idx + 3 + 1)
> + return -1;
> +
> + /* Flash offset - lower 24 bits */
> + addr = (tx[idx] << 16) | (tx[idx + 1] << 8) | tx[idx + 2];
> +
> + /* Flash offset - upper 8 bits */
> + if (priv->mode_4byte)
> + addr |= tx[1] << 24;
> +
> + /* Remaining length for data (excluding one dummy cycle) */
> + bytes -= idx + 3 + 1;
> + if (rx)
> + rx += idx + 3 + 1;
> +
> + /* non-aligned transfers are handled by MSPI */
> + if (!DWORD_ALIGNED(addr))
> + return -1;
> +
> + bcmspi_enable_bspi(priv);
> + /* Record BSPI status */
> + priv->bspi_addr = addr;
> + }
> +
> + /* Transfer data if any */
> + while (bytes && rx) {
> + /* Special handing since RAF cannot go across 16MB boundary */
> + uint trans = bytes;
> +
> + /*
> + * Divide into multiple transfers if it goes
> + * across the boundary
> + */
> + if (priv->mode_4byte &&
> + (priv->bspi_addr >> 24) !=
> + ((priv->bspi_addr + bytes) >> 24)) {
> + /*
> + * Limit this transfer to not go beyond
> + * 16MB boundary
> + */
> + trans = 0x1000000 - (priv->bspi_addr & 0xFFFFFF);
> + }
> + bspi_read_via_raf(priv, rx, trans);
> + priv->bspi_addr += trans;
> + rx += trans;
> + bytes -= trans;
> + }
> +
> + /* Flush prefetch buffers at the end */
> + if (flags & SPI_XFER_END)
> + bspi_flush_prefetch_buffers(priv);
> +
> + return 0;
> +}
> +
> +static int bspi_xfer(struct bcmspi_priv *priv, const u8 *tx, u8 *rx,
> + uint bytes, ulong flags)
> +{
> + /* Check if we can make use of BSPI */
> + if (flags & SPI_XFER_BEGIN) {
> + if (bytes) {
> + if (bspi_read(priv, tx, rx, bytes, flags) == 0)
> + return 0;
> + }
> + } else if (priv->state == QSPI_STATE_BSPI) {
> + if (bspi_read(priv, tx, rx, bytes, flags) == 0)
> + return 0;
> + }
> +
> + /* continue in mspi mode */
> + return 1;
> +}
> +
> +static int mspi_xfer(struct bcmspi_priv *priv, uint bytes,
> + const u8 *tx, u8 *rx, ulong flags)
> +{
> + u32 cdr = CDRAM_PCS0;
> +
> + if (flags & XFER_QUAD) {
> + cdr |= CDRAM_QUAD_MODE;
> +
> + if (!tx)
> + cdr |= CDRAM_RBIT_INPUT;
> + }
> +
> + if (bytes & 1) {
> + /* Use 8-bit queue for odd-bytes transfer */
> + if (priv->mspi_16bit) {
> + setbits_le32(priv->mspi + MSPI_SPCR0_MSB_REG,
> + MSPI_SPCR0_MSB_BITS_8);
> + priv->mspi_16bit = 0;
> + }
> + } else {
> + /* Use 16-bit queue for even-bytes transfer */
> + if (!priv->mspi_16bit) {
> + clrbits_le32(priv->mspi + MSPI_SPCR0_MSB_REG,
> + MSPI_SPCR0_MSB_BITS_8);
> + priv->mspi_16bit = 1;
> + }
> + }
> +
> + while (bytes) {
> + uint chunk;
> + uint queues;
> + ulong start;
> + uint i;
> +
> + /* Separate code for 16bit and 8bit transfers for performance
> */
> + if (priv->mspi_16bit) {
> + /* Determine how many bytes to process this time */
> + chunk = min(bytes, NUM_CDRAM * 2);
> + queues = (chunk - 1) / 2 + 1;
> + bytes -= chunk;
> +
> + /* Fill CDRAMs */
> + for (i = 0; i < queues; i++)
> + writel(cdr | CDRAM_CONT | CDRAM_BITS_EN,
> + priv->mspi + MSPI_CDRAM_REG + (i <<
> 2));
> +
> + /* Fill TXRAMs */
> + for (i = 0; i < chunk; i++)
> + writel(tx ? tx[i] : 0xff,
> + priv->mspi + MSPI_TXRAM_REG + (i <<
> 2));
> + } else {
> + /* Determine how many bytes to process this time */
> + chunk = min(bytes, NUM_CDRAM);
> + queues = chunk;
> + bytes -= chunk;
> +
> + /* Fill CDRAMs and TXRAMS */
> + for (i = 0; i < chunk; i++) {
> + writel(cdr | CDRAM_CONT,
> + priv->mspi + MSPI_CDRAM_REG + (i <<
> 2));
> + writel(tx ? tx[i] : 0xff,
> + priv->mspi + MSPI_TXRAM_REG + (i <<
> 3));
> + }
> + }
> +
> + /* Setup queue pointers */
> + writel(0, priv->mspi + MSPI_NEWQP_REG);
> + writel(queues - 1, priv->mspi + MSPI_ENDQP_REG);
> +
> + /* Deassert CS if requested and it's the last transfer */
> + if (bytes == 0 && (flags & SPI_XFER_END))
> + clrbits_le32(priv->mspi + MSPI_CDRAM_REG +
> + ((queues - 1) << 2), CDRAM_CONT);
> +
> + /* Kick off */
> + writel(0, priv->mspi + MSPI_STATUS_REG);
> + if (bytes == 0 && (flags & SPI_XFER_END))
> + writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG);
> + else
> + writel(MSPI_SPE | MSPI_CONT_AFTER_CMD,
> + priv->mspi + MSPI_SPCR2_REG);
> +
> + /* Wait for completion */
> + start = get_timer(0);
> + while (get_timer(start) <
> + QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
> + if (readl(priv->mspi + MSPI_STATUS_REG) & 1)
> + break;
> + }
> + if ((readl(priv->mspi + MSPI_STATUS_REG) & 1) == 0)
> + return -1;
> +
> + /* Read data out */
> + if (rx) {
> + if (priv->mspi_16bit) {
> + for (i = 0; i < chunk; i++) {
> + rx[i] = readl(priv->mspi +
> + MSPI_RXRAM_REG +
> + (i << 2)) & 0xff;
> + }
> + } else {
> + for (i = 0; i < chunk; i++) {
> + rx[i] = readl(priv->mspi +
> + MSPI_RXRAM_REG +
> + (((i << 1) + 1) << 2))
> + & 0xff;
> + }
> + }
> + }
> +
> + /* Advance pointers */
> + if (tx)
> + tx += chunk;
> + if (rx)
> + rx += chunk;
> + }
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + uint spbr;
> +
> + priv->max_hz = speed;
> +
> + /* MSPI: SCK configuration */
> + spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
> + writel(max(min(spbr, SPBR_MAX), SPBR_MIN),
> + priv->mspi + MSPI_SPCR0_LSB_REG);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + u32 data_lanes;
> +
> + priv->spi_mode = mode;
> +
> + if (mode & SPI_RX_QUAD)
> + data_lanes = 4;
> + else if (mode & SPI_RX_DUAL)
> + data_lanes = 2;
> + else
> + data_lanes = 1;
> +
> + if (data_lanes != 1) {
> + /* BSPI: configure for dual/quad mode */
> + writel(0, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
> + writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
> + /* Dummy cycles */
> + setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG,
> + IPROC_BSPI_READ_DUMMY_CYCLES);
> + /* Override the strap settings */
> + setbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 << BSPI_STRAP_OVERRIDE_SHIFT);
> + /*
> + * Configure following based on QUAD/DUAL mode
> + * - data_quad or data_dual_n_sgl
> + * - data_bpc select
> + * - bspi_cmd_byte
> + */
> + if (data_lanes == 4) {
> + setbits_le32(priv->bspi +
> BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 <<
> BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT);
> + clrbits_le32(priv->bspi +
> BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 <<
> BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT);
> + setbits_le32(priv->bspi + BSPI_BITS_PER_CYCLE_REG,
> + 2 << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
> + writel(IPROC_BSPI_READ_CMD4,
> + priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
> + } else if (data_lanes == 2) {
> + clrbits_le32(priv->bspi +
> BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 <<
> BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT);
> + setbits_le32(priv->bspi +
> BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 <<
> BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT);
> + setbits_le32(priv->bspi + BSPI_BITS_PER_CYCLE_REG,
> + 1 << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
> + writel(IPROC_BSPI_READ_CMD2,
> + priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
> + }
> + /* Enable flex mode to take effect */
> + writel(FLEX_MODE_ENABLE_BIT, priv->bspi +
> + BSPI_FLEX_MODE_ENABLE_REG);
> + } else {
> + /* configure BSPI for single mode */
> + writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
> + writel(0, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
> + /* Dummy cycles */
> + setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG,
> + IPROC_BSPI_READ_DUMMY_CYCLES);
> + /* clear strap override, data_dual_n_sgl and data_quad bits */
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 << BSPI_STRAP_OVERRIDE_SHIFT);
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT);
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + 1 << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT);
> + writel(IPROC_BSPI_READ_CMD,
> + priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
> + }
> +
> + /*
> + * MSPI: Mode configuration (8 bits by default)
> + * MSPI supports only single mode.
> + */
> + priv->mspi_16bit = 0;
> + writel(0x80 | /* Master */
> + (8 << 2) | /* 8 bits per word */
> + (priv->spi_mode & 3), /* mode: CPOL / CPHA */
> + priv->mspi + MSPI_SPCR0_MSB_REG);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_claim_bus(struct udevice *dev)
> +{
> + /* nothing to do */
> + return 0;
> +}
> +
> +static int iproc_qspi_release_bus(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> +
> + /* Make sure no operation is in progress */
> + writel(0, priv->mspi + MSPI_SPCR2_REG);
> + udelay(1);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_xfer(struct udevice *dev, uint bitlen,
> + const void *dout, void *din, ulong flags)
> +{
> + struct udevice *bus = dev->parent;
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + const u8 *tx = dout;
> + u8 *rx = din;
> + uint bytes = bitlen / 8;
> + int ret = 0;
> +
> + /* we can only do 8 bit transfers */
> + if (bitlen % 8)
> + return -1;
> +
> + if (priv->use_bspi) {
> + ret = bspi_xfer(priv, tx, rx, bytes, flags);
> + if (ret <= 0)
> + return ret;
> + }
> +
> + /* MSPI: Enable write lock at the beginning */
> + if (flags & SPI_XFER_BEGIN) {
> + /* Switch to MSPI if not yet */
> + if (bcmspi_disable_bspi(priv) != 0)
> + return -1;
> +
> + writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG);
> + }
> +
> + /* MSPI: Transfer it */
> + if (bytes)
> + ret = mspi_xfer(priv, bytes, tx, rx, flags);
> +
> + /* MSPI: Disable write lock if it's done */
> + if (flags & SPI_XFER_END) {
> + writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
> + /* Switch back to BSPI */
> + if (priv->use_bspi)
> + writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
> + }
> +
> + return ret;
> +}
> +
> +static int iproc_qspi_ofdata_to_platdata(struct udevice *bus)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + ofnode subnode;
> +
> + priv->bspi = (void __iomem *)dev_read_addr_name(bus, "bspi");
> + if (IS_ERR(priv->bspi)) {
> + debug("%s: Failed to get bspi base address\n", __func__);
> + return PTR_ERR(priv->bspi);
> + }
> +
> + priv->bspi_raf = (void __iomem *)dev_read_addr_name(bus, "bspi_raf");
> + if (IS_ERR(priv->bspi_raf)) {
> + debug("%s: Failed to get bspi_raf base address\n", __func__);
> + return PTR_ERR(priv->bspi_raf);
> + }
> +
> + priv->mspi = (void __iomem *)dev_read_addr_name(bus, "mspi");
> + if (IS_ERR(priv->mspi)) {
> + debug("%s: Failed to get mspi base address\n", __func__);
> + return PTR_ERR(priv->mspi);
> + }
> +
> + subnode = dev_read_first_subnode(bus);
> + if (ofnode_valid(subnode))
> + priv->frequency = ofnode_read_u32_default(subnode,
> + "spi-max-frequency",
> + QSPI_DEF_SCK_FREQ);
> + else
> + priv->frequency = QSPI_DEF_SCK_FREQ;
> +
> + priv->use_bspi = dev_read_u32_default(bus, "use-bspi", 0);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_probe(struct udevice *bus)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> +
> + priv->mode_4byte = 0;
> + /* MSPI: Basic hardware initialization */
> + writel(0, priv->mspi + MSPI_SPCR1_LSB_REG);
> + writel(0, priv->mspi + MSPI_SPCR1_MSB_REG);
> + writel(0, priv->mspi + MSPI_NEWQP_REG);
> + writel(0, priv->mspi + MSPI_ENDQP_REG);
> + writel(0, priv->mspi + MSPI_SPCR2_REG);
> +
> + if (priv->use_bspi) {
> + bcmspi_enable_bspi(priv);
> + } else {
> + if (bcmspi_disable_bspi(priv)) {
> + printf("Failed to set in MSPI mode\n");
> + return -1;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct dm_spi_ops iproc_qspi_ops = {
> + .claim_bus = iproc_qspi_claim_bus,
> + .release_bus = iproc_qspi_release_bus,
> + .xfer = iproc_qspi_xfer,
> + .set_speed = iproc_qspi_set_speed,
> + .set_mode = iproc_qspi_set_mode,
> +};
> +
> +static const struct udevice_id iproc_qspi_ids[] = {
> + { .compatible = "brcm,iproc-qspi" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(iproc_qspi) = {
> + .name = "iproc_qspi",
> + .id = UCLASS_SPI,
> + .of_match = iproc_qspi_ids,
> + .ops = &iproc_qspi_ops,
> + .of_to_plat = iproc_qspi_ofdata_to_platdata,
> + .priv_auto = sizeof(struct bcmspi_priv),
> + .probe = iproc_qspi_probe,
> +};
> diff --git a/drivers/spi/iproc_qspi.h b/drivers/spi/iproc_qspi.h
> new file mode 100644
> index 000000000000..6f1218c959ce
> --- /dev/null
> +++ b/drivers/spi/iproc_qspi.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2020-2021 Broadcom
> + */
> +
> +#include <spi.h>
> +
> +#ifndef _IPROC_QSPI_H_
> +#define _IPROC_QSPI_H_
> +
> +/*SPI configuration enable*/
> +#define IPROC_QSPI_BUS 0
> +#define IPROC_QSPI_CS 0
> +
Look like the previous comments are not resolved still.
> +#define IPROC_BSPI_READ_CMD 0x0b
SPINOR_OP_READ_FAST
> +#define IPROC_BSPI_READ_CMD2 0x3b
SPINOR_OP_READ_1_1_2
> +#define IPROC_BSPI_READ_CMD4 0x6b
SPINOR_OP_READ_1_1_4
> +#define IPROC_BSPI_READ_DUMMY_CYCLES 0x08
Flash dummy cycles.
If the controller purely a flash specific, add it in mtd side.
drivers/spi is for spi controller drivers.
Jagan.
