On 8/27/21 7:55 AM, Michal Simek wrote:
TTC has three modes of operations. Timer, PWM and input counters.
There is already driver for timer under CADENCE_TTC_TIMER which is used for
ZynqMP R5 configuration.
This driver is targeting PWM which is for example configuration which can
be used for fan control.
The driver has been tested on Xilinx Kria SOM platform where fan is
connected to one PL pin. When TTC output is connected via EMIO to PL pin
TTC pwm can be configured and tested for example like this:
pwm config 0 0 10000 1200
pwm enable 0 0
pwm config 0 0 10000 1400
pwm config 0 0 10000 1600
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
MAINTAINERS | 1 +
drivers/pwm/Kconfig | 7 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-cadence-ttc.c | 217 ++++++++++++++++++++++++++++++++++
4 files changed, 226 insertions(+)
create mode 100644 drivers/pwm/pwm-cadence-ttc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cf0c33c5d58..889813382249 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -600,6 +600,7 @@ F: drivers/mmc/zynq_sdhci.c
F: drivers/mtd/nand/raw/zynq_nand.c
F: drivers/net/phy/xilinx_phy.c
F: drivers/net/zynq_gem.c
+F: drivers/pwm/pwm-cadence-ttc.c
F: drivers/serial/serial_zynq.c
F: drivers/reset/reset-zynqmp.c
F: drivers/rtc/zynqmp_rtc.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cf7f4c6840ce..176e703c8fbb 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,13 @@ config DM_PWM
frequency/period can be controlled along with the proportion of that
time that the signal is high.
+config PWM_CADENCE_TTC
+ bool "Enable support for the Cadence TTC PWM"
+ depends on DM_PWM && !CADENCE_TTC_TIMER
+ help
+ Cadence TTC can be configured as timer which is done via
+ CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now.
+
config PWM_CROS_EC
bool "Enable support for the Chrome OS EC PWM"
depends on DM_PWM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 10d244bfb79d..abf5af41d2cc 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c
new file mode 100644
index 000000000000..1d007676bb3b
--- /dev/null
+++ b/drivers/pwm/pwm-cadence-ttc.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 Xilinx, Inc. Michal Simek
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <log.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <log.h>
+#include <div64.h>
+#include <linux/math64.h>
+#include <linux/log2.h>
+#include <dm/device_compat.h>
+
+#define TTC_COUNTER_CONTROL_1 0xc
+#define TTC_INTERVAL_COUNTER_1 0x24
+#define TTC_MATCH_1_COUNTER_1 0x30
+
+#define CPWM_CLK_FALLING_EDGE 0x40
BIT(6)
+#define CPWM_CLK_SRC_EXTERNAL 0x20
BIT(5)
+#define CPWM_CLK_PRESCALE_SHIFT 1
+#define CPWM_CLK_PRESCALE_MASK (15 << 1)
GENMASK(4, 1)
+#define CPWM_CLK_PRESCALE_ENABLE 1
Why CPWM_? And please use register names which match the datasheet. E.g.
XXX_EX_E instead of XXX_FALLING_EDGE.
+
+#define CPWM_COUNTER_CTRL_WAVE_POL 0x40
+#define CPWM_COUNTER_CTRL_WAVE_DISABLE 0x20
+#define CPWM_COUNTER_CTRL_RESET 0x10
+#define CPWM_COUNTER_CTRL_MATCH_ENABLE 0x8
+#define CPWM_COUNTER_CTRL_DECREMENT_ENABLE 0x4
+#define CPWM_COUNTER_CTRL_INTERVAL_ENABLE 0x2
+#define CPWM_COUNTER_CTRL_COUNTING_DISABLE 0x1
ditto
+
+struct cadence_ttc_pwm_priv {
+ uchar *regs;
+ unsigned long frequency;
+ bool invert[2];
+};
+
+static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ priv->invert[channel] = polarity;
+
+ dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
+
+ return 0;
+}
+
+static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+ u32 counter_ctrl, x;
+ int period_clocks, duty_clocks, prescaler;
+
+ dev_dbg(dev, "channel %d, duty %d/ period %d ns\n", channel,
+ duty_ns, period_ns);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ /* Make sure counter is stopped */
Shouldn't this be a write? And do we even need to check for this?
+ counter_ctrl = readl(priv->regs + TTC_COUNTER_CONTROL_1 +
+ (channel * 4));
You may want to add a macro for this. e.g.
#define TTC_COUNTER_CONTROL(channel) (TTC_COUNTER_CONTROL_1 + channel *
sizeof(u32))
and similarly for the other macros
+ setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4),
+ CPWM_COUNTER_CTRL_COUNTING_DISABLE);
+
+ /* Calculate period, prescaler and set clock control register */
+ period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
+ 1000000000LL);
Please use NSEC_PER_SEC.
+
+ prescaler = ilog2(period_clocks) + 1 - 16;
+ if (prescaler < 0)
+ prescaler = 0;
+
+ x = readl(priv->regs + (channel * 4));
Please use a define for TTC_CLOCK_CONTROL. And please use descriptive
variable names.
+
+ if (!prescaler) {
+ x &= ~(CPWM_CLK_PRESCALE_ENABLE | CPWM_CLK_PRESCALE_MASK);
+ } else {
+ x &= ~CPWM_CLK_PRESCALE_MASK;
+ x |= CPWM_CLK_PRESCALE_ENABLE |
+ (((prescaler - 1) << CPWM_CLK_PRESCALE_SHIFT) &
+ CPWM_CLK_PRESCALE_MASK);
Use FIELD_PREP here.
+ };
+
+ /* External source is not handled by this driver now */
+ x &= ~CPWM_CLK_SRC_EXTERNAL;
+
+ writel(x, priv->regs + (channel * 4));
+ /* Calculate interval and set counter control value */
+ duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
+ 1000000000LL);
+
+ writel((period_clocks >> prescaler) & 0xffff,
+ priv->regs + TTC_INTERVAL_COUNTER_1 + (channel * 4));
Please read timer-width from the device tree to select the proper mask.
This also determines the magic value 16 for the prescaler above.
+ writel((duty_clocks >> prescaler) & 0xffff,
+ priv->regs + TTC_MATCH_1_COUNTER_1 + (channel * 4));
ditto
+
+ /* Restore counter */
Perhaps "Reset counter"?
+ counter_ctrl &= ~CPWM_COUNTER_CTRL_DECREMENT_ENABLE;
+ counter_ctrl |= CPWM_COUNTER_CTRL_INTERVAL_ENABLE |
+ CPWM_COUNTER_CTRL_RESET |
+ CPWM_COUNTER_CTRL_MATCH_ENABLE;
+
+ if (priv->invert[channel])
+ counter_ctrl |= CPWM_COUNTER_CTRL_WAVE_POL;
+ else
+ counter_ctrl &= ~CPWM_COUNTER_CTRL_WAVE_POL;
+
+ writel(counter_ctrl,
+ priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4));
+
+ dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
+ period_clocks, prescaler);
+
+ return 0;
+};
+
+static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
+ bool enable)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+
+ if (channel > 2) {
+ dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
+
+ if (enable) {
+ clrbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4),
+ CPWM_COUNTER_CTRL_COUNTING_DISABLE |
+ CPWM_COUNTER_CTRL_WAVE_DISABLE);
+ setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4),
+ CPWM_COUNTER_CTRL_RESET);
+ } else {
+ setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4),
+ CPWM_COUNTER_CTRL_COUNTING_DISABLE |
+ CPWM_COUNTER_CTRL_WAVE_DISABLE);
+ }
+
+ return 0;
+};
+
+static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int cadence_ttc_pwm_probe(struct udevice *dev)
+{
+ struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
Shouldn't there be a check for #pwm-cells somewhere in here to ensure
that the correct driver gets bound?
--Sean
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ priv->frequency = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(priv->frequency)) {
+ dev_err(dev, "failed to get rate\n");
+ return priv->frequency;
+ }
+ dev_dbg(dev, "Clk frequency: %ld\n", __func__, priv->frequency);
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pwm_ops cadence_ttc_pwm_ops = {
+ .set_invert = cadence_ttc_pwm_set_invert,
+ .set_config = cadence_ttc_pwm_set_config,
+ .set_enable = cadence_ttc_pwm_set_enable,
+};
+
+static const struct udevice_id cadence_ttc_pwm_ids[] = {
+ { .compatible = "cdns,ttc" },
+ { }
+};
+
+U_BOOT_DRIVER(cadence_ttc_pwm) = {
+ .name = "cadence_ttc_pwm",
+ .id = UCLASS_PWM,
+ .of_match = cadence_ttc_pwm_ids,
+ .ops = &cadence_ttc_pwm_ops,
+ .of_to_plat = cadence_ttc_pwm_of_to_plat,
+ .probe = cadence_ttc_pwm_probe,
+ .priv_auto = sizeof(struct cadence_ttc_pwm_priv),
+};
