Hi, This series contains several fixes for TI j721e and j7200 platforms data and also some fixes for TI clock drivers that make use of this data.
All fixes are related to PLL post dividers reporting the wrong frequency, and now the new frequencies for below clocks match what registers are actually configured for. Clock: Old Frequency -> New Frequency ----------------------------------------- postdiv2_16fft_main_0_hsdivout6_clk: 66666667 -> 200000000 postdiv2_16fft_main_1_hsdivout5_clk: 320000000 -> 960000000 postdiv2_16fft_main_1_hsdivout7_clk: 320000000 -> 960000000 Regards, Dave Dave Gerlach (2): arm: mach-k3: Add note to auto-generated files clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write Suman Anna (3): arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks clk: ti: k3: Update driver to account for divider flags arch/arm/mach-k3/j7200/clk-data.c | 87 ++++++++++++----------- arch/arm/mach-k3/j7200/dev-data.c | 2 + arch/arm/mach-k3/j721e/clk-data.c | 113 +++++++++++++++--------------- arch/arm/mach-k3/j721e/dev-data.c | 2 + drivers/clk/ti/clk-k3-pll.c | 13 +++- drivers/clk/ti/clk-k3.c | 4 +- include/k3-clk.h | 30 ++++---- 7 files changed, 137 insertions(+), 114 deletions(-) -- 2.28.0
