Hi Bin,
On Sat, 31 Jul 2021 at 02:45, Bin Meng <bmeng...@gmail.com> wrote:
>
> This actually reverts the following 2 commits:
>
> commit 427911001809 ("x86: Set up the MTRR for SDRAM")
> commit d46c0932a9d4 ("x86: fsp: Adjust calculations for MTRR range and DRAM
> top")
>
> There are several outstanding issues as to why:
>
> * For FSP1, the system memory and reserved memory used by FSP are
> already programmed in the MTRR by FSP.
> * The 'mtrr_top' mistakenly includes TSEG memory range that has the
> same RES_MEM_RESERVED resource type. Its address is programmed
> and reported by FSP to be near the top of 4 GiB space, which is
> not what we want for SDRAM.
> * The call to mtrr_add_request() is not guaranteed to have its size
> to be exactly the power of 2. This causes reserved bits of the
> IA32_MTRR_PHYSMASK register to be written which generates #GP.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
> ---
>
> arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++-------------------------
> 1 file changed, 10 insertions(+), 25 deletions(-)
Unfortunately this makes coral (FSP2) go *very* slowly. Can you
perhaps do this change just for FSP1?
Regards,
Simon
