On Wed, Jun 9, 2021 at 3:55 PM Bin Meng <bmeng...@gmail.com> wrote: > > Current logic in riscv_get_ipi() for Andes PLICSW does not look good > to me. The mask to test IPI pending bits for a hart should be left > shifted by (8 * gd->arch.boot_hart), just the same as what is done in > riscv_send_ipi(). > > Signed-off-by: Bin Meng <bmeng...@gmail.com> > > --- > It looks there is no datasheet released from Andes that describes how > PLICSW works, and its register fields. I can only get an understanding > from current U-Boot and OpenSBI PLICSW driver. > > This requires testing on Andes hardware, which I don't have access to. > > arch/riscv/lib/andes_plic.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) >
Ping?
